Zynq UltraScale＋ MPSoC VCU TRD 2019.2 - SDI Video Capture and SDI Display with PLDDR

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The below table gives information about the features supported in this design. 

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There exist some bus messages to let you know about the clock and clock providers in the pipeline. You can see what clock is selected in the pipeline by looking at the NEW_CLOCK message on the bus. When a clock provider is removed from the pipeline, a CLOCK_LOST message is posted and the application should go to PAUSED and back to PLAYING to select a new clock.

For more detail please refer: https://gstreamer.freedesktop.org/documentation/application-development/advanced/clocks.html?gi-language=c

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3 Appendix A - Input Configuration File (input.cfg)

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