The purpose of this page is to describe the Linux V4L2 driver for the Xilinx DisplayPort 1.4 RX Subsystem Soft IP for Zynq UltraScale+ MPSoC and for Versal.

Note: The content of this page is applicable for the 2022.1 release. A few steps for building the kernel or taking sources from Git might be different for previous releases before 2022.1.

Table of Contents

Introduction

The DisplayPort (DP) 1.4 Receiver Subsystem is a plug-in solution for serial digital video data reception in large Video systems of up to video resolutions of Full Ultra HD (FUHD) at 30 fps.

It has the dynamic support of BPC (Bits per pixel) and different color formats. DisplayPort ( DP) 1.4 core supports 4 data lanes and each lane supports dynamic data rate up to 8.1Gb/s. It is a feature-rich soft IP incorporating all the necessary logic to properly interface with PHY layers and provide DP decoding functionality. The subsystem is a hierarchical IP that bundles a collection of DP RX-related IP sub-cores and outputs them as a single IP. The subsystem outputs multi-pixel video to AXI4-Stream Protocol interface. Below is the block diagram of the DisplayPort 1.4 Rx Subsystem.

Figure 1. Block diagram of the DisplayPort 1.4 Rx subsystem

DP Rx interface with Video PHY Controller for Zynq UltraScale+ MPSoC

Figure 2. Block diagram of MAC interface with PHY for Zynq

DP Rx interface with GT Quad base Controller for Versal

The DP 1.4 Receiver Subsystem is a MAC subsystem which works with a GT Quad Base Controller (PHY) to create a video connectivity system. The DP 1.4 Receiver Subsystem is tightly coupled with the Xilinx PHY Controller, which itself is independent and offers flexible architecture with multiple-protocol support. Both the MAC and PHY are dynamically programmable through the AXI4-Lite interface.

Figure 3. Block diagram of MAC interface with PHY for Versal

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• 2020.1 : dp-modules/Documentation/devicetree/bindings/xlnx,v-dp-rx-ss.txt - Deprecated 

2020.2 : https://github.com/XilinxDocumentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2021.1 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2021.2 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml - Deprecated 

2022.1 : Documentation  Documentation/devicetree/bindings/displaymedia/xlnxxilinx/xlnx,dpv-txdprxss.yaml

2023.2 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

2024.1 : Documentation/devicetree/bindings/media/xilinx/xlnx,v-dprxss.yaml

Building Driver Modules in OSL flow

Note: The below steps are applicable for building images for 2020.1. These steps are deprecated. Customers are advised to use 2022.1 onwards drivers and the device tree.

• Create a directory to build driver modules in local machine.
  • example : mkdir build_dir
• clone the linux-xlnx from git https://github.com/Xilinx/linux-xlnx.git  to build_dir.
  • cd build_dir
  • git clone  https://github.com/Xilinx/linux-xlnx.git
• Clone the  dp-modules to build_dir directory
  • git clone https://github.com/Xilinx/dp-modules.git
• create a directory for the kernel output
  • mkdir kernel_output

• Create a make file and copy the below contents to it

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• 2024.1
  • Summary:

    • e7228b8c v4l: xilinx: dprx: Replace irq_of_parse_and_map with platform_get_irq_by_name

    • 75fc0b5 v4l: xilinx: dprx: Correct the XDPRX_DEVICE_SERVICE_IRQ_CP_IRQ_MASK mask value
    • ddc46b1 v4l: xilinx: dprxss: Fix cppcheck warnings 
    • f244a29 v4l: xilinx: dprx: Fix lane count allowed range of values
•  2023.2
  • Summary:
    • a89e660 v4l2: xilinx: dprx: Add HDCP2x support
    • 022d9d3 v4l: xilinx: dprx: Remove 0x200 obsolete register usage
    • 3733d2a  v4l: xilinx: Add interface type parameter to HDCP initialize function
    • 42f7575 v4l2: xilinx: dprx: Add support for YUV 420 8bpc and 10bpc color format
    • 4a511ba v4l: xilinx: dprx: Correct the XDPRX_HPD_INTR_MASK macro bit mask value
    • 650d180 v4l: xilinx: dprx: Add check for status1 in irq_handler
    • 5ad0c90 v4l2: xilinx: dprx: Move the interrupt handlers to workqueue

• 2023.1
  • Summary:
    • 4a511ba v4l: xilinx: dprx: Correct the XDPRX_HPD_INTR_MASK macro bit mask value
    • 650d180 v4l: xilinx: dprx: Add check for status1 in irq_handler
    • 5ad0c90 v4l2: xilinx: dprx: Move the interrupt handlers to workqueue
•  2022.2
  • Summary:
    •  d7d99e0: v4l: xilinx: dprx: Fix dtg enable register update
    • cfdc4cd v4l: xilinx: dprx: Add support for static HDR
    • 66853f8  v4l: xilinx: dprx: Enable audio to receive infoframes with static HDR…
    • 47ba8cf  v4l: xilinx: dprx: Fix compilation error
    • 9b6c5df  v4l: xilinx: dprx: Add HDCP1X support
•  2022.1
  • Summary:
    • f2e88a581130 v4l: xilinx: dprxss: Add support for Versal
    • 9b62852ec04b Merge tag 'v5.15' into master
    • 986aca58b142 v4l: xilinx: dprx: Disable unplug interrupt when RX is disconnected
    • f6d1241bb3c4 v4l: xilinx: dprx: Fix typo in macro
    • a83d69b2d8e2 v4l: xilinx: dprx: Generate HPD interrupt in unplug handler
    • 535e3c204208 v4l: xilinx: dprx: Disable audio when training is lost
    • 7e01e94bf687 v4l: xilinx: dprx: Correct the DTG disable sequence
    • f0462a9ebeae v4l: xilinx: dprx: Update max linkrate to extended capability registers
    • 1241f0ac2c23 v4l: xilinx: dprx: Set default CDR timeout value
    • 8ebfdae0ac5e v4l: xilinx: dprx: Enable training timeout
    • caf59ff90799 v4l: xilinx: dprxss: Add changes to get gt_quad_base as phy handle
    • 5f68e6129b68 v4l: xilinx: dprx: Align kernel-doc description
    • 94c6af3e9c95 v4l: xilinx: dprx: Call retimer reset functions
    • 40653103453e v4l: xilinx: dprx: Reset the retimer dp data path
    • be37b4278bb3 v4l: xilinx: dprx: Fix TP2 macro
    • d534ae1bf76f v4l: xilinx: dprx: Implement access laneset and tp2 interrupt handlers
    • 647c103aaa52 v4l: xilinx: dprx: Implement prbs7 mode enable in retimer
    • 9f2b813b6fc2 v4l: xilinx: dprx: Implement prbs7 mode enable in video phy
    • 96feaf25679d v4l: xilinx: dprx: Enable training related interrupts in unplug handler
    • f63eb4c6a2fd v4l: xilinx: dprx: Enable audio interrupts in no video handler
    • 001e0c6bf4f9 v4l: xilinx: dprx: Enable or disable INTERRUPT_CAUSE_1 interrupts
    • 70f52b12363f v4l: xilinx: dprx: Add support for 8k 25fps resolution
    • 5ff7cd8defe1 v4l: xilinx: dprx: Update video timings information
    • 50fc7aacbe25 v4l: xilinx: dprx: Add MMCM configuration for rx_dec_clk for versal systems
    • 7628155 v4l: xilinx: dprx: Add unplug handler function in work queue
•  2021.2
  • Summary:
    • 9d3bae6d6871 v4l: xilinx: Added support for DP audio
    • 7a1899cdc9db v4l: xilinx: dprxss: Remove double which word

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