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This page gives an overview of the bare-metal driver support for the Octal SPI controller.

Table of Contents

Table of Contents
excludeTable of Contents

Introduction

The octal SPI (OSPI) controller can access one or two flash devices using several different methods. The controller is located with the other flash memory controllers in the PMC. The I/O
interface is routed to the PMC MIO pin bank 0. OSPI is commonly used as a boot device. The controller provides multiple ways to read and write the flash memory:
• STIG/PIO read/write (software triggered instruction generator)
• Direct read/write with address remap
• Non-DMA indirect read/write via AXI slave interface
• DMA indirect read using AXI master interface

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The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

ospipsv

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/ospipsv

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv

Info

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/ospipsv

The driver source code is organized into different folders.  The table below shows the ospipsv driver source organization. 

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl , .mdd and .yaml files

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter refer Chapter 73: Octal SPI Controller in Versal TRM

Features

  1. Software triggered IO mode (STIG) up to 8-bytes of data transfers.

  2. Indirect DMA reads.

  3. Local SRAM to reduce AHB overhead.

  4. Supports SDR and DDR protocols.

  5. Programmable master mode clock frequencies.

  6. Programmable peripheral selects (chip select).

  7. Support for Single and Octal instructions.

  8. Interrupts and polled based operations.

Known Issues and Limitations

  • Macronix flash works only up to 150MHz.

Supported Flash vendors

  • Micron

  • ISSI

  • Gigadevice

  • Macronix

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

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Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examples

Test Name

Example Source

Description

OSPI Polled mode example

xospipsv_flash_polled_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Polled mode.

OSPI Interrupt mode example

xospipsv_flash_intr_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Interrupt mode.

OSPI Non-blocking Polled mode example

xospipsv_flash_non_blocking_read_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Non-blocking Polled mode.

Example Application Usage

...

Example Design Architecture

NA

Performance

At frequency 133.33 MHz

DDR mode:

Read Speed: 253371 KBPS

SDR-PHY mode: 

Read Speed: 128849 KBPS

At frequency 33.33 MHz

SDR NON-PHY mode:

Read Speed: 32625 KBPS

Change Log

2024.2

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https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L118

Related Links

Note

xospipsv_flash_polled_example.c and xospipsv_flash_intr_example.c are reference for flash support for different vendors and rest all examples are reference for controller/driver features.