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This page provides all the information related to Design Module 1 - VCU TRD
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Muti Stream design.
Table of Contents
| Table of Contents | ||
|---|---|---|
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1 Overview
The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks.
This design supports the following video interfaces:
Sources:
- Test pattern generator (TPG) implemented in the PL.
- HDMI-Rx capture pipeline implemented in the PL.
- MIPI CSI-2 Rx capture pipeline implemented in the PL.
- File source (SD card, USB storage, SATA hard disk).
- Stream-In from network or internet.
Sinks:
- DP Tx display pipeline in the PS.
- HDMI-Tx display pipeline implemented in the PL.
VCU Codec:
- Video Encode/Decode capability using VCU hard block in PL
- AVC/HEVC encoding
- Encoder/decoder parameter configuration.
- Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput
Streaming Interfaces:
- 1G Ethernet PS GEM
Video format:
- NV12
The below figure shows the TRD block diagram.
- Demonstrate the multi-stream capability of VCU at 4k 60 Hz throughput.
- Supports 2-4KP30 multi-stream feature with any 2 of HDMI-Rx, TPG, and MIPI as the input source and HDMI-Tx as display pipeline.
- Supports 4-1080p60 multi-stream feature with 3 HDMI-Rx and 1 MIPI as the input source and HDMI-Tx as display pipeline.
- Supports 8-1080p30 multi-stream feature with 7 HDMI-Rx and 1 MIPI as the input source and HDMI-Tx as display pipeline.
Other features:
- This design supports 8 channel memory based SCD(Scene Change Detection) IP. SCD can be enabled or disabled through configuration
Supported Resolution:
The table below provides the supported resolution from GUI and command line app in this design.
| Resolution | GUI | Command Line | |
| Single Stream | Single Stream | Multi-stream | |
| 4kp60 | X | √ | NA |
| 4kp30 | √ | √ | √ (Max 2) |
| 1080p60 | √ | √ | √ (Max 4) |
| 1080p30 | X | √ | √ (Max 8) |
√ - Supported
NA – Not applicable
x – Not supported
The below table gives information about the features supported in this design.
| Pipeline | Input source | Output Type | Resolution | VCU codec |
|---|---|---|---|---|
Capture--> Display(Passthrough pipeline) | HDMI-Rx/MIPI/TPG | HDMI-Tx/DP | 4KP/1080p | None |
Single Stream: Capture--> SCD --> Encode--> Decode--> Display | HDMI-Rx/MIPI/TPG | HDMI-Tx/DP | 4KP/1080p | HEVC/AVC |
Multi-Stream (2 input sources): Capture--> SCD --> Encode--> Decode--> Display | HDMI-Rx/MIPI/TPG | HDMI-Tx | 4KP30 | HEVC/AVC |
Multi-Stream(4 input sources): Capture--> SCD --> Encode--> Decode--> Display | HDMI-Rx/MIPI/TPG | HDMI-Tx | 1080P60 | HEVC/AVC |
| Multi-Stream(8 input sources): Capture--> SCD --> Encode--> Decode--> Display | 7-HDMI-Rx + 1 MIPI | HDMI-Tx | 1080P30 | HEVC/AVC |
Single Stream: Record/Stream-Out pipeline | HDMI-Rx/MIPI/TPG | File Sink/ Stream-Out | 4K/1080p | HEVC/AVC |
Multi-Stream(2 or 4 i/p sources): Record/Stream-Out pipeline | HDMI-Rx/MIPI/TPG | File Sink/ Stream-Out | 2-4KP30/4-1080p60 | HEVC/AVC |
Multi-Stream(8 input sources): Record/Stream-Out pipeline | 7-HDMI-Rx + 1 MIPI | File Sink/ Stream-Out | 8-1080P30 | HEVC/AVC |
File/Streaming Playback pipeline | File Source/ Stream-In | HDMI-Tx/DP | 4K/1080p | HEVC/AVC |
NOTE: DP will support a max resolution of 4KP30
TPG will not support 1080P30 resolution mode.
The below figure shows the VCU TRD design hardware block diagram.
The below figure shows the VCU TRD design software block diagram.
1.1 Board Setup
Refer below link for Board Setup
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