...

The software architecture for this design is shown in Figure 5. The driver is divided into the following sections.

• Initialization

• MAC driver hooks

• Interrupt service routines

References

1. AXI 1G/2.5G Ethernet Subsystem v7.0 Product Guide (PG138)

2. 1G/2.5G Ethernet PCS/PMA or SGMII v16.0 LogiCORE IP Product Guide (PG047)

3. 10G/25G High Speed Ethernet Subsystem v2.0 Product Guide (PG210)

4. PS and PL based Ethernet in Zynq MPSoC

5. Si570 Data Sheet (www.silabs.com/Support%20Documents/TechnicalDocs/Si570.pdf)

6. AXI DMA v7.1 LogiCORE IP Product Guide (PG021)

7. Netperf(www.netperf.org)

8. iPerf (http://sourceforge.net/projects/iperf/)

9. Xilinx Vivado Design Suite

10. PetaLinux

11. Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)

12. ZCU102 Evaluation Board User Guide (UG1182)13.UltraScale Architecture GTH Transceivers User Guide (UG576)