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Before the execution of vcu_gst_app, we need to check the HDMI-Rx or SDI-Rx link status depending on the design. Refer to Appendix B for HDMI-Rx and or SDI-Rx link status-up issue.
Before the execution of vcu_gst_app, we need to check the HDMI-Tx or SDI-Tx link and CRTC configurations depending on the design. Refer to Appendix B for the HDMI-Tx or SDI-Tx link-up the issue.
Execution of the application is shown below:
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Design | Project | hardware design name |
VCU TRD | VCU TRD | zcu106_trd |
Multistream Audio Video Design | HDMI-Rx + VCU + HDMI-Tx + Audio and | zc106_audio |
SDI Capture and Display with PL DDR | SDI-Rx + VCU + SDI-Tx + Audio + PLDDRPL DDR | zcu106_picxo_plddr_sdi |
PL DDR HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR | zcu106_plddr_hdmi |
VCU PCIe | VCU PCIe | zcu106_pcie |
VCU 10g | VCU 10g | zcu106_10g |
HDMI Capture | HDMI-Rx + VCU | zcu106_hdmirx |
HDMI Display | VCU + HDMI-Tx | zcu106_hdmitx |
SDI Capture | SDI Rx + VCU | zcu106_sdirx |
SDI Display | VCU + SDI Tx | zcu106_sditx |
Xilinx Low Latency PS DDR NV12 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP+Audio | zcu106_llp2_audio_nv12 |
Xilinx Low Latency PL DDR NV16 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_nv16 |
Xilinx Low Latency PL DDR XV20 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_xv20 |
Xilinx Low Latency PL DDR XV20 SDI Capture and Display | SDI-Rx + VCU + SDI-Tx + PLDDR PL DDR + Sync IP | zcu106_picxo_llp2_sdi |
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This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
PetaLinux Installation: Refer to the PetaLinux Tools Documentation UG1144 Link will be added <June-05> for installation.
It is recommended to follow the build steps in sequence.
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Design | Project | XSA file |
VCU TRD | VCU TRD | zcu106_trd_wrapper.xsa |
Multistream Audio | HDMI-Rx + VCU + HDMI-Tx + Audio and | zcu106_audio_wrapper.xsa |
10G Ethernet Video streaming | 10G HDMI-Rx + VCU + HDMI-Tx | zcu106_10g_wrapper.xsa |
SDI Capture and Display with Audio | SDI-Rx + VCU + SDI-Tx + Audio + PLDDRPL DDR | zcu106_picxo_plddr_sdi_wrapper.xsa |
HDMI Video Capture | HDMI-Rx + VCU | zcu106_hdmirx_wrapper.xsa |
HDMI Video Display | VCU + HDMI-Tx | zcu106_hdmitx_wrapper.xsa |
SDI Video Capture | SDI-Rx + VCU | zcu106_sdirx_wrapper.xsa |
SDI Video Display | VCU + SDI-Tx | zcu106_sditx_wrapper.xsa |
PL DDR HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR | zcu106_plddr_hdmi_wrapper.xsa |
PCIe Encode, Decode and Transcode | PCIe XDMA + VCU | zcu106_pcie_wrapper.xsa |
Xilinx Low Latency PS DDR NV12 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | zcu106_llp2_audio_nv12_wrapper.xsa |
Xilinx Low Latency PL DDR NV16 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_nv16_wrapper.xsa |
Xilinx Low Latency PL DDR XV20 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | zcu106_llp2_xv20_wrapper.xsa |
Xilinx Low Latency PL DDR XV20 SDI Capture and Display | SDI-Rx + VCU + SDI-Tx + PLDDR PL DDR + SYNC IP | zcu106_picxo_llp2_sdi_wrapper.xsa |
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Design | Project | dtsi |
|---|---|---|
VCU TRD | VCU TRD | vcu_trd.dtsi |
Multistream Audio | HDMI-Rx + VCU + HDMI-Tx + Audio and | vcu_audio.dtsi |
10G Ethernet Video streaming | 10G HDMI-Rx + VCU + HDMI-Tx | vcu_10g.dtsi |
PL DDR SDI Capture and Display with Audio | SDI-Rx + VCU + SDI-Tx + PLDDRPL DDR | vcu_plddr_sdi.dtsi |
HDMI Video Capture | HDMI-Rx + VCU | vcu_hdmirx.dtsi |
HDMI Video Display | VCU + HDMI-Tx | vcu_hdmitx.dtsi |
SDI Video Capture | SDI-Rx + VCU | vcu_sdirx.dtsi |
SDI Video Display | VCU + SDI-Tx | vcu_sditx.dtsi |
PL DDR HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR | vcu_plddr_hdmi.dtsi |
PCIe Encode, Decode and Transcode | PCIe XDMA + VCU | vcu_pcie.dtsi |
Xilinx Low Latency PS DDR NV12 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | vcu_llp2_psddr_hdmi.dtsi |
Xilinx Low Latency PL DDR NV16 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_plddr_hdmi_nv16.dtsi |
Xilinx Low Latency PL DDR XV20 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_plddr_hdmi_xv20.dtsi |
Xilinx Low Latency PL DDR XV20 SDI Capture and Display | SDI-Rx + VCU + SDI-Tx + PLDDR PL DDR + SYNC IP | vcu_llp2_plddr_sdi.dtsi |
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Custom EDID Support
The TRD design is tested/validated with ABOX 2017 and NVIDIA SHIELD Pro. If you want to try with any new HDMI source, you need to generate the EDID of the new source and update it in the TRD bsp. Refer to Custom EDID Support for adding the newly generated EDID file.
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Design | Project | Image Path |
VCU TRD | VCU TRD | vcu_multistream_nv12 |
Multistream Audio | HDMI-Rx + VCU + HDMI-Tx + Audio | vcu_audio |
10G Ethernet Video streaming | 10G HDMI-Rx + VCU + HDMI-Tx | vcu_10g |
PLDDR SDI Capture and Display with Audio | SDI-Rx + VCU + SDI-Tx + AUDIO + PLDDRPL DDR | vcu_sdi_xv20 |
HDMI Video Capture | HDMI-Rx + VCU | vcu_hdmi_rx |
HDMI Video Display | VCU + HDMI-Tx | vcu_hdmi_tx |
SDI Video Capture | SDI-Rx + VCU | vcu_sdirx |
SDI Video Display | VCU + SDI-Tx | vcu_sditx |
PL DDR HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR | vcu_hdmi_multistream_xv20 |
PCIe Encode, Decode and Transcode | PCIe XDMA + VCU | vcu_pcie |
Xilinx Low Latency PS DDR NV12 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + Sync IP + Audio | vcu_llp2_hdmi_nv12 |
Xilinx Low Latency PL DDR NV16 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_hdmi_nv16 |
Xilinx Low Latency PL DDR XV20 HDMI Capture and Display | HDMI-Rx + VCU + HDMI-Tx + PL DDR + Sync IP | vcu_llp2_hdmi_xv20 |
Xilinx Low Latency PL DDR XV20 SDI Capture and Display | SDI-Rx + VCU + SDI-Tx + PLDDR PL DDR + SYNC IP | vcu_llp2_sdi_xv20 |
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