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Table of Contents


Note: xilinx_devcfg.c driver got deprecated in 2018.1 release and Added FPGA manager support for zynq platform.

xilinx_devcfg.c driver was implemented in character driver model it support only Bitstream loading using sysfs entries
it will not support the other functionality supported by the Fpga Manager framework.
Use ZYNQ FPGA manager to program Bitstream into Zynq PL
http://www.wiki.xilinx.com/Solution+Zynq+PL+Programming+With+FPGA+Manager

Introduction

The Zynq Programmable Logic (PL) can be programmed by the First Stage Bootloader (FSBL), U-Boot or through Linux. Programming the PL at different stages may be advantageous for different projects and workflows.

HW IP Features

  • It support full-bitstream and partial Bitstream loading.
  • It support Encrypted and Authenticated Bitstream loading.

Features supported in driver

  • It supports full-bitstream Bitstream loading.

Known Issues and Limitations

  • No support for partial Bitstream loading.
  • No support for Authenticated Bitstream loading.
  • No support for Encrypted Bitstream loading.

Kernel Configuration

Device Drivers ---> Character devices ---> <*> Xilinx Device Configuration



Devicetree

Code Block
themeMidnight
devcfg: devcfg@f8007000 {
                        compatible = "xlnx,zynq-devcfg-1.0";
                        interrupt-parent = <&&intc>;
                        interrupts = <0 8 4>;
                        reg = <0xf8007000 0x100>;
                        clocks = <&&clkc 12>, <&&clkc 15>, <&&clkc 16>, <&&clkc 17>, <&&clkc 18>;
                        clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
                        syscon = <&&slcr>;
                };

Task Dependencies (Pre-requisites)



Tools Required


Input Files Required




Test procedure

Programming ZYNQ PL through Linux

Once booted into Linux, write the bitstream file to the devcfg device:
Code Block
themeMidnight
$cat bitstream.bit > /dev/xdevcfg
Programming the PL through the FSBL
The First Stage Boot-Loader (FSBL) is capable of programming the PL before loading U-Boot, which may be necessary for some applications. To have the FSBL load the PL, include the bitstream file when generating boot.bin and boot normally.
References:

Programming the PL through U-Boot

Load the bitstream into memory and then use fpga loadb to program the PL; for example:
Code Block
themeMidnight
U-Boot> fatload mmc 0 0x4000000 bitstream.bit
U-Boot> fpga loadb 0 0x4000000 <bitstream file size>

Expected Output

Linux:
After, the prog_done file should indicate that the programming was successful.
Code Block
themeMidnight
$ cat /sys/class/xdevcfg/xdevcfg/device/prog_done
1

Mainline Status

  • This driver is Not available at Mainline.

Change Log

2016.3
Summary:
  • char: devcfg: Add bitstream version check.
Commits:
  • 50d2141 char: devcfg: Add bitstream version check.

2016.4
  • None

2017.1
Summary:
  • Revert "char: devcfg: Add bitstream version check"
Commits:
  • 7e2120a Revert "char: devcfg: Add bitstream version check"

2017.2
  • None

2017.3
Summary:
  • char: xilinx_devcfg: Fix kernel doc warnings
  • char: xilinx_devcfg: Fix warnings in the driver
  • char: xilinx_devcfg: Remove xilinx_devcfg.h header
  • char: xdevcfg: remove unneeded PCFG_PROG_B assertion
Commits:
  • e43ad17 char: xilinx_devcfg: Fix kernel doc warnings
  • c390fee char: xilinx_devcfg: Fix warnings in the driver
  • 96e6444 char: xilinx_devcfg: Remove xilinx_devcfg.h header
  • 991325b char: xdevcfg: remove unneeded PCFG_PROG_B assertion

2017.4
Summary:
  • char: xilinx_devcfg: Fix regression.
Commits:
  • 8823e00char: xilinx_devcfg: Fix regression.

Related Links