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• zynqmp-clk-ccf.dtsi has static clock node configuration, if user wants to change any of the clock information update those in system-user.dtsi.
• Multi concat Interrupt blocks wont be supported by the DTG.
• DTG doesn't support IP that are packaged in a subsystem(multiple BD's)
• Interrupt port width more than one wont be supported.
• When multicore is enabled for the MAC IPs(if the MAC IPs are more than 1) then there is issue with the label in DTG and it fails. But there wont be an issue if the MAC IP is one and multicore is enabled.
• DTG wont support for generation of private peripheral interrupts(PPI).
• DTG supports the video pipeline generation based on the internal TRD designs as mentioned in the wiki https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/25329832/Zynq+UltraScale+MPSoC+VCU+TRD+2018.3
• DTG doesn't support custom IP, For Multimedia use case If there are any custom IPs connected between the video pipeline IPs DTG wont support those, user may need to add the input and output ports.
• For broadcaster IP the output can connect to multiple output ports and DTG cant know which output port is a valid for the correct pipeline.
• If there are multiple similar video pipelines in the design user need to add the input and output port information in the nodes. The below wiki gives some info about how to add the input and output ports.
• DTG doesn't support non memory-mapped IP's.
• DTG limitation for multimedia IPs
• In DFX flow designs if we have any pl gpio ip and if we use standalone xsct commands to generate the dtsi files or dtbo then "gpio-cells" is setting to 3. It should be 2 from kernel 5.15 version on. Please set this "gpio-cells" to 2. We will fix this in 2022.2 release
• With the current DTG implementation not able to populate the ttc timer properties in pcw.dtsi even if the design has ttc ips. In board dtsi file zynq-7000.dtsi/zynqmp.dtsi/versal.dtsi change the ttc timer name to ttctimer then you will see the entries in pcw.dtsi. We will fix this in 2022.2 release.
• when there are multi ethernet ips in the zynqmp design then getting syntax error for the third IP. Closing the clock with ">" resolves the issue in pl.dtsi file

New Features for 2022.1:

• Added mrmac IP initial support.
• Added DPU IP support
• Replaced the hardcoded values with the macros for reset and power.
• Added dma channels for axi_mcdma IP support in DTG.
• Generate the memory node for each axi_noc IP for Versal
• Added dfx support in DTG
• generating the aie clock node for versal designs if they have aie ip.
• For aie node you can find the detailed doc in below
• https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/soc/xilinx/xlnx%2Cai-engine.yaml 

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Using HSI commands
1.Clone the device tree repo
https://github.com/Xilinx/device-tree-xlnx
2) Go to the HSI prompt
[vabbarap@xhdl3763 /proj/xhdsswstaff/vabbarap/Overlay/New_hdf> % hsi
hsi v2017.3 (64-bit)SW Build 2018833 on Wed Oct 4 19:58:07 MDT 2017
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
3)
hsi% open_hw_design system.hdf
4)
hsi% set_repo_path /home/vabbarap/workspace/sync_dt_tip/clk_wiz_15_12_2017 (DTG repo path)
5)
hsi% create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree
6)
hsi% set_property CONFIG.dt_overlay true [get_os]
7)
hsi% generate_target -dir dt/
hsi% ls dt/
pcw.dtsi pl.dtsi sd22.mss system-top.dts zynqmp-clk-ccf.dtsi zynqmp.dtsi

Using XSCT (From 2019.2 release no hsi support)

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3) hsi open_hw_design system.xsa

4) hsi set_repo_path /home/vabbarap/workspace/sync_dt_tip/dt_15_12_2019 (DTG repo path)

5) hsi create_sw_design -proc psu_cortexa53_0 sd22 -os device_tree 

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