Table of Contents
Introduction

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RF-ADC Features

Tile configuration
- Four RF-ADCs and one PLL per tile
- 12-bit RF-ADC resolution, with 16-bit digital signal processing datapath
- Implemented as either four channels of 2 GSPS, or two channels of 4 GSPS (device dependent).
Decimation filters
- 1x (bypass filter), 2x, 4x, 8x
- 80% of Nyquist bandwidth, 89 dB stop-band attenuation.
Digital Complex Mixers
- Full complex mixers support real or I/Q inputs from the ADCs
- 48-bit Numeric Controlled Oscillator (NCO) per RF-ADC
- Fixed Fs/4, Fs/2 low power frequency mixing mode, where Fs is the sample frequency
- I/Q and real input signals supported.
Single/multi-band flexibility
- 2x bands per 2 GSPS RF-ADC pair
- Can be configured for real or I/Q inputs.
Full bandwidth of the RF-ADC at 4 GSPS can be accessed in bypass mode.
Input signal amplitude threshold: Two programmable threshold flags per RF-ADC
Built-in digital correction for external analog quadrature modulators:
- Supports gain, phase, and offset correction for and I/Q input pair (two RF-ADCs).
SYSREF input signal for multi-channel synchronization.
Flexible AXI4-Stream interface supports a wide range of programmable logic clock rates and converter sample rates.
Per tile current-mode logic (CML) clock input buffer with on-chip calibrated 100 Ù termination; supplies the RF-ADC sampling clocks or provides a reference clock for the on-chip PLL.
Dedicated high-speed, high-performance, differential input buffer per RF-ADC with on-chip calibrated 100 Ù termination (on-die termination).
Output common mode reference voltage for DC coupling RF-ADC inputs

RF-DAC Features

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Four RF-DACs and one PLL per tile
14-bit RF-DAC resolution with 16-bit digital signal processing path
Sampling speed 6.4 GSPS per RF-DAC
4 GHz full power output bandwidth

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1x (bypass filter), 2x, 4x, 8x
80% pass band, 89 dB stop band attenuation

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Full complex mixers support real or I/Q output signals to the DACs
48-bit NCO per RF-DAC
Fixed Fs/4, Fs/2 low-power frequency mixing mode
Supports mixed mode RF-DAC functionality which maximizes RF-DAC power in the second Nyquist zone

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2x bands per RF-DAC pair
Can be configured for real or I/Q outputs

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Supports gain, phase, and offset correction for an I/Q output pair (2 RF-DACs)

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Test Cases

xrfdc_intr_example.c –

For the RFSoC Data Converter, the interrupts are mostly used for error reporting.
The interrupts do not do any data processing. Since they don’t do any data processing, interrupts are invoked in rare conditions.
The example here attempts to demonstrate users how an error interrupt can be generated. Also once generated how does the processing happen. Upon an interrupt, the control reaches to ScuGIC interrupt handler. From there the control is transferred to the libmetal isr handling which then calls the driver interrupt handler. Users are expected to register their callbacks with the driver interrupt framework.
The actual interrupt handling is expected to happen in the user provided callback.
This example generates ADC fabric interrupts by writing some incorrect fabric data rate based on the read/write clocks.

xrfdc_selftest_example.c

This example does some writes to the hardware to do some sanity checks and does a reset to restore the original settings

xrfdc_read_write_example.c

This example uses multiple driver "set" APIs to configure the targeted AMS block. Subsequently it uses "get" APIs to read back the configurations to ensure that the desired configurations are applied.
For DAC it sets the following configurations:
MixerSettings, QMCSettings, Write Fabricrate, Decoder mode, Output Current and Coarse Delay.
For ADC it sets the following configurations:
MixerSettings, QMCSettings, Read Fabricrate and Threshold Settings.
This example shows how to change the configurations for ADC and DAC using driver functions.

xrfdc_mts_example.c

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Changelog

2019.2

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Added support for DAC variable output power for GEN 3 devices

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2019.1

New interpolaton & decimation modes (IP dependent)
New Image Reject Filter (IP dependent)
New DAC modes (IP dependent)
Second Nyquist zone inerse sinc filter (IP dependent)
Support for alternative DAC bondout (IP dependent)
New ADC signal detector (IP dependent)
New calibration override APIs (IP dependent)
Extended coarse delay (IP dependent)
New clock distribution network with integer clock division(IP dependent)
New Common mode over/under interrupts (IP dependent)
Interrupt APIs now return standard error codes (exempt XRFdc_IntrHandler and XRFdc_SetStatusHandler)
XRFdc_DynamicPLLConfig now only restarts a tile if it was on previously

2018.3.1

Now get maximum FS from IP
Determinig ADC Type now on a per-tile basis
The wrong fabric rate was being used for a 2GSPS ADC at a decimation rate of 8.The wrong fabric rate was being used for a 2GSPS ADC at a decimation rate of 8
The paramater "DataType" is now "MixerInputDataType"
Added APIs to set and get IM3 Dither.

2018.3

Updated DAC min sampling rate to 500MHz and also update VCO Range, PLL_DIVIDER and PLL_FPDIV ranges.
Added XRFdc_GetFabClkOutDiv() API to read fabric clk div.
Added Inline APIs XRFdc_CheckBlockEnabled(), XRFdc_CheckTileEnabled(), XRFdc_CheckDigitalPathEnabled(), XRFdc_IsADCDigitalPathEnabled(), XRFdc_GetMultibandConfig() and XRFdc_IsDACDigitalPathEnabled()
Fixed Multiband crossbar settings in C2C mode.
Updated Mixer_Settings structure.
Added MixerType member to MixerSettings structure and Update Mixer Settings APIs to consider the MixerType variable.
Removed __MICROBLAZE__ defines and use libmetal interface for Microblaze.
Added support to read the REFCLKDIV param from design.
Added XRFDC_MIXER_MODE_R2R option to support BYPASS mode for Real input.
Update powerup-state value based on PLL mode in XRFdc_DynamicPLLConfig() API.
Update XRFdc_SetPLLConfig() API to support range of REF_CLK_DIV values(1 to 4).
Updated StartUp, Shutdown and Reset APIs.

2018.2

Added XRFdc_MTS_Sysref_Config API to enable/disable sysref.
Updated max VCO value to 13108MHz to support max DAC sample rate of 6.554MHz.
Adjusted calculated latency by sysref period, where doing so results in closer alignment to the target latency.
Enabled VCO Auto selection while configuring the clock.
Added XRFdc_GetPLLConfig() API to get PLL Configurations.
Added XRFdc_GetLinkCoupling() API to get the Link Coupling mode.
Added clock configuration files for ZCU111 in examples.
Updated the lmk configuration to support different revisions of zcu111.
Added support for configuring lmx 5.12GHz
Removed CalibrationMode check for DAC in XRFdc_GetMixerSettings() and XRFdc_GetNyquistZone() APIs.
Updated lower limit of Ref clock to 102.40625MHz.

2018.1

Added XRFdc_SetInterpolationFactor() and XRFdc_SetDecimationFactor() APIs.
Added CoarseMixMode field in mixer settings.
Added XRFdc_SetCalibrationMode() and XRFdc_GetCalibrationMode() APIs for calibration modes switch.
Added XRFdc_DynamicPLLConfig() API for PLL and external clock switch support.
Added XRFdc_GetClockSource() API to get clock source.
Added XRFdc_GetPLLLockStatus() API to get PLL lock status.
Added XRFdc_GetDriverVersion() API to get the driver version.
Added XRFdc_MultiConverter_Sync() and XRFdc_MultiConverter_Init() APIs to support Multi-Tile Sync.
Added XRFdc_SetInvSincFIR() and XRFdc_GetInvSincFIR() APIs to support inverse-sinc.
Added XRFdc_MultiBand() and XRFdc_SetSignalFlow() APIs to configure Multiband and Singleband.
Updated PLL structure in XRFdc_DynamicPLLConfig() API.
Added support for Marker event source for DAC block.
Added support for reloading DTC scans.
Added option to configure sysref capture after MTS.

2017.4

Fixed XRFdc_GetNoOfADCBlocks API issue in 4GSPS
Enable decoder clock based on decoder mode
Added API to get current FIFO status
Added support for 4GSPS CoarseMixer frequency
Modified float datatypes to double
Fixed ADCBlockEnable API in 4GSPS
Fixed Set Threshold API
Fixed PhaseOffset truncation issue
Provided user configurability for Mixer scale
Return error for invalid mixer modes
Corrected FIFO and DATA interrupt masks
Fixed startup, shutdown and Reset API's for TileId -1

Introduction

Provide high-level introduction for the IP

The Xilinx® LogiCORE™ IP Zynq® UltraScale+™ RFSoC RF Data Converter IP core provides a configurable wrapper to allow the RF-DAC and RF-ADC blocks to be used in IP integrator designs.

For more information, please refer to https://www.xilinx.com/products/boards-and-kits/zcu208.html , https://www.xilinx.com/products/boards-and-kits/zcu216.html & https://www.xilinx.com/products/boards-and-kits/zcu111.html .

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github
rfdc	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/rfdc_v10_0	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is:

https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/rfdc

The driver source code is organized into different folders. The table below shows the <Driver Name> driver source organization.

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl and .mdd file
examples	Example applications that show how to use the driver features
src	Driver source files

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc/examples

Test Name	Example Source	Description
Self Test	xrfdc_selftest_example.c	This example does some writes to the hardware to do some sanity checks.
Read/Write Test	xrfdc_read_write_example.c	This example uses multiple driver "set" APIs to configure the targeted* AMS block.* Subsequently it uses "get" APIs to read back the configurations to ensure that the desired configurations are applied.
Multi Tile Sync Example	xrfdc_mts_example.c	This example demonstrates the multi-tile sync functionality
Interrupt Example	xrfdc_intr_example.c	This example shows the interrupts working
Clocked Gen 3 Example	xrfdc_gen3_clocked_example.c	This example shows how to set the clocks for Gen 3 devices
Clocked Gen 2 Example	xrfdc_gen2_or_below_clocked_example.c	This example shows how to set the clocks for Gen 3 devices

Example Application Usage

Self Test

This example does some writes to the hardware to do some sanity checks.

Expected Output

RFdc Selftest Example Test
Successfully ran Selftest Example Test

Read/Write Test

This example does some writes to the hardware to do some sanity checks.

Expected Output

RFdc Read and Write Example Test

 DAC00 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC00 Output Current is 32025mA

 ADC00 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 ADC00: Link Coupling Mode is 1

 DAC01 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC01 Output Current is 32025mA

 ADC01 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 ADC01: Link Coupling Mode is 1

 DAC02 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC02 Output Current is 32025mA

 DAC03 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC03 Output Current is 32025mA

 ADC0 PLL Configurations:: PLL Enable is 1      Feedback Divider is 48  OutputDivider is 6      ReferenceClk Divider is 1

 DAC0 PLL Configurations:: PLL Enable is 1      Feedback Divider is 32  OutputDivider is 2      ReferenceClk Divider is 1

 DAC10 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC10 Output Current is 32025mA

 ADC10 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 ADC10: Link Coupling Mode is 1

 DAC11 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC11 Output Current is 32025mA

 DAC12 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC12 Output Current is 32025mA

 DAC13 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 DAC13 Output Current is 32025mA

 ADC1 PLL Configurations:: PLL Enable is 1      Feedback Divider is 48  OutputDivider is 6      ReferenceClk Divider is 1

 DAC1 PLL Configurations:: PLL Enable is 1      Feedback Divider is 32  OutputDivider is 2      ReferenceClk Divider is 1

 ADC20 Status
DataPathClockStatus - 1          IsFIFOFlagsEnabled - 3          IsFIFOFlagsAsserted - 0

 ADC20: Link Coupling Mode is 1

 ADC2 PLL Configurations:: PLL Enable is 1      Feedback Divider is 48  OutputDivider is 3      ReferenceClk Divider is 1
=======Default DigitalDataPath Configuration for Tile0======

 DAC DigitalDataPath0-> Connected I data = 0
 DAC DigitalDataPath0-> Connected Q data = -1
 ADC DigitalDataPath0-> Connected I data = 0
 ADC DigitalDataPath0-> Connected Q data = -1
 DAC DigitalDataPath1-> Connected I data = 1
 DAC DigitalDataPath1-> Connected Q data = -1
 ADC DigitalDataPath1-> Connected I data = 1
 ADC DigitalDataPath1-> Connected Q data = -1
 DAC DigitalDataPath2-> Connected I data = 2
 DAC DigitalDataPath2-> Connected Q data = -1
 ADC DigitalDataPath2-> Connected I data = 2
 ADC DigitalDataPath2-> Connected Q data = -1
 DAC DigitalDataPath3-> Connected I data = 3
 DAC DigitalDataPath3-> Connected Q data = -1
 ADC DigitalDataPath3-> Connected I data = 3
 ADC DigitalDataPath3-> Connected Q data = -1
 ADC0 MB Config is 0

 DAC0 MB Config is 0

 ============================================
=============ADC0-4G SB Configuration R2C==========

 ADC DigitalDataPath0-> Connected I data = 0
 ADC DigitalDataPath0-> Connected Q data = -1
 ADC DigitalDataPath1-> Connected I data = 1
 ADC DigitalDataPath1-> Connected Q data = -1
 ADC DigitalDataPath2-> Connected I data = 2
 ADC DigitalDataPath2-> Connected Q data = -1
 ADC DigitalDataPath3-> Connected I data = 3
 ADC DigitalDataPath3-> Connected Q data = -1
 ADC0 MB Config is 0

 ================================================
=============ADC0,1-4G MB Configuration R2C==========

 ADC DigitalDataPath0-> Connected I data = 0
 ADC DigitalDataPath0-> Connected Q data = -1
 ADC DigitalDataPath1-> Connected I data = 0
 ADC DigitalDataPath1-> Connected Q data = -1
 ADC DigitalDataPath2-> Connected I data = 2
 ADC DigitalDataPath2-> Connected Q data = -1
 ADC DigitalDataPath3-> Connected I data = 3
 ADC DigitalDataPath3-> Connected Q data = -1
 ADC0 MB Config is 1

 ================================================
=============ADC0,1-4G MB Configuration C2C==========

 ADC DigitalDataPath0-> Connected I data = 0
 ADC DigitalDataPath0-> Connected Q data = 1
 ADC DigitalDataPath1-> Connected I data = 0
 ADC DigitalDataPath1-> Connected Q data = 1
 ADC DigitalDataPath2-> Connected I data = 2
 ADC DigitalDataPath2-> Connected Q data = -1
 ADC DigitalDataPath3-> Connected I data = 3
 ADC DigitalDataPath3-> Connected Q data = -1
 ADC0 MB Config is 1

 ================================================
=============ADC0,1-4G SB Configuration R2C==========

 ADC DigitalDataPath0-> Connected I data = 0
 ADC DigitalDataPath0-> Connected Q data = -1
 ADC DigitalDataPath1-> Connected I data = 1
 ADC DigitalDataPath1-> Connected Q data = -1
 ADC DigitalDataPath2-> Connected I data = 2
 ADC DigitalDataPath2-> Connected Q data = -1
 ADC DigitalDataPath3-> Connected I data = 3
 ADC DigitalDataPath3-> Connected Q data = -1
 ADC0 MB Config is 0

 ================================================
=============DAC0 SB Configuration C2R==========

 DAC DigitalDataPath0-> Connected I data = 0
 DAC DigitalDataPath0-> Connected Q data = -1
 DAC DigitalDataPath1-> Connected I data = 1
 DAC DigitalDataPath1-> Connected Q data = -1
 DAC DigitalDataPath2-> Connected I data = 2
 DAC DigitalDataPath2-> Connected Q data = -1
 DAC DigitalDataPath3-> Connected I data = 3
 DAC DigitalDataPath3-> Connected Q data = -1
 DAC0 MB Config is 0

 ============================================

 DAC2,3 MB Config is 2

 DAC 4X MB Config is 4

 DAC0,1 MB Config is 3

 DAC2,3 MB Config is 3

 DAC0, 1 SB Config is 2

 DAC2, 3 SB Config is 0
Successfully ran Read and Write Example

Interrupt Example

This example does some writes to the hardware to do some sanity checks.

Expected Output

RFdc Fabric Interrupt Example Test
registered stim block.
registered cap block.
registered IPI interrupt.
Waiting for Interrupt


 Successfully ran RFdc Fabric Interrupt Example Test

Change Log

https://github.com/Xilinx/embeddedsw/commits/master/XilinxProcessorIPLib/drivers/rfdc

Versions Compared

Old Version 14

New Version 15

Key

Table of Contents
Introduction

RF-ADC Features

RF-DAC Features

Test Cases

Changelog

2019.2

2019.1

2018.3.1

2018.3

2018.2

2018.1

2017.4

Related Links

Table of Contents

Introduction

Driver Sources

Example Applications

Links to Examples

Example Application Usage

Self Test

Read/Write Test

Interrupt Example

Change Log

Related Links

Page Comparison

Versions Compared

Old Version 14

New Version 15

Key

RF-ADC Features

RF-DAC Features

Test Cases

Changelog

2019.2

2019.1

2018.3.1

2018.3

2018.2

2018.1

2017.4

Related Links

Table of Contents

Introduction

Driver Sources

Example Applications

Links to Examples

Example Application Usage

Self Test

Read/Write Test

Interrupt Example

Change Log

Related Links