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Missing Features, Known Issues and Limitations

• None

Kernel Configuration

Device Drivers --->[*] Reset Controller Support--->[*] Xilinx ZYNQMP Reset Controller Support

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$echo  reset_IP_num > /sys/class/reset-mgr/reset    ----> It will reset the IP by providing the  High  to low signal.
$echo reset_IP_num > /sys/class/reset-mgr/reset_assert  ---> it will assert IP by providing the HIGH signal ( the relevant bit is set to High until it receives deassert signal).
$echo reset_IP_num > /sys/class/reset-mgr/reset_deassert  ---> it will deassert IP by providing the LOW signal

Mainline Status

This driver is

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in Mainline.

Fixes related to coverity warnings are not yet in mainline (~2 lines)

Change Log

2016.3
Summary:

• reset: reset-zynqmp: Adding support for Xilinx zynqmp reset controller.

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2019.1

• Sync Mainline changes

  • reset: reset-zynqmp: Sync Reset Id macro with Mainline
  • reset: reset-zynqmp: Move eemi_ops inside zynqmp_reset_data struct
  • reset: reset-zynqmp: Defer probe if firmware is not ready
  • reset: reset-zynqmp: License fix and copyright update
  • reset: reset-zynqmp: Removed license text

2019.2

• None

2020.1

• None

2020.2

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