Axi Ethernet Linux driver for Microblaze, Zynq, Zynq Ultrascale+ MPSoC and Versal

Introduction

HW IP features

AXI 1G/2.5G Ethernet Subsystem (PG138)

Support for MII, GMII, RGMII, SGMII, and 1000BASE-X PHY interfaces
Support for 1000BASE-X and SGMII over select Input/Output (I/O) low voltage differential signaling (LVDS)
Support for pause frames for flow control
Media Independent Interface Management
Ethernet Audio Video Bridging (AVB) support
AXI4-Stream transmit/receive interface
Support for 2.5G Ethernet
IEEE Standard 1588 Support
AXI4-Lite register interface

10 Gigabit Ethernet subsystem (PG157)

Designed to 10 Gigabit Ethernet specification IEEE Standard 802.3-2012
AXI4-Stream protocol support on client TX and RX interfaces
Configured and monitored through an optional AXI4-Lite Management Data interface or using status and configuration vectors
Supports 10GBASE-SR, -LR and -ER optical links in Zynq-7000, UltraScale™, Virtex-7, and Kintex-7 devices (LAN mode only)
Supports 10GBASE-KR backplane links including Auto-Negotiation (AN), Training and Forward Error Correction (FEC)
Supports Deficit Idle Count
Comprehensive statistics gathering
Supports 802.3 and 802.1Qbb flow control
Supports VLAN and jumbo frames
Custom Preamble mode
Independent TX and RX Maximum Transmission Unit (MTU) frame length
Supports high accuracy IEEE Standard 1588-2008 1-step and 2-step timestamping on a 10GBASE-R network interface

10G/25G Ethernet Subsystem (PG210)

Designed to the Ethernet requirements for 10/25 Gb/s operation specified by IEEE 802.3 Clause 49, IEEE 802.3by, and the 25G Ethernet Consortium
Includes complete Ethernet MAC and PCS/PMA functions or standalone PCS/PMA for 25Gb/s operation
Includes complete Ethernet MAC and PCS/PMA functions, standalone MAC or standalone PCS/PMA for 10 Gb/s operation
Simple packet-oriented user interface
Comprehensive statistics gathering
Status signals for all major functional indicators
BASE-R PCS sublayer operating at 10.3125Gb/s or 25.78125Gb/s
Optional clause 74 BASE-KR FEC sublayer
Optional Auto-Negotiation
Optional clause 108 25G Reed-Solomon Forward Error Correction (RS-FEC) sublayer
Custom Preamble mode
Optional IEEE 1588 1-step and 2-step timestamping
Runtime switchable between 10G and 25G

USXGMII Ethernet Subsystem (PG251)

Designed to meet the USXGMII specification EDCS-1467841 revision 1.4
Supports 10M, 100M, 1G, 2.5G, 5G, or 10GE data rates over a 10.3125 Gb/s link
Both media access control (MAC) and PCS/PMA functions are included
Code replication/removal of lower rates onto the 10GE link
Rate adaption onto user clock domain
Low data path latency
32-bit AXI4-Stream interface for datapath
Optional AXI4-Lite register interface
Support for 802.3x and priority-based pause operation
Detailed statistics gathering
Support for custom preambles
Supports deficit idle count (DIC)

MRMAC Ethernet Subsystem (PG251)

Hardened Ethernet IP block on Versal.
Multi rate Ethernet MAC supporting speeds from 10G to 100G.
- The driver supports 25GE and 10GE with 1 to 4 lanes.
Hardened IP (to be used with Soft DMA and logic for driver subsystems)
High performance, low latency.
Low data path latency
User-side AXI4-Stream interface for data
AXI4-Lite register interface
Detailed statistics gathering
IEEE1588 support

Features supported in the driver

Support ethernet IPs- AXI 1G/2.5G Ethernet subsystem (PG138), 10G Ethernet subsystem(PG157), 10G Ethernet Subsystem(PG210), USXGMII(PG251) and MRMAC.
IEEE 1588 Support for 1G and legacy 10G MAC (PG157), 10G Ethernet subsystem(PG210) and MRMAC
Speed support for 10/100/1000 Mbps for 1G MAC
10G Base-R support for Legacy 10G MAC(PG157) and 10G MAC (PG210)
10G and 25G speed support for MRMAC
Support for GMII/RGMII/SGMII/1000Base-X Phy Configurations
Supports Independent 4K, 8K, 16K, or 32KB TX and RX frame buffer memory
Support for common ethtool queries.
NAPI support.
Full/Partial Checksum offload support
Support for Jumbo Frames
Supports AXI DMA and AXI MCDMA dma configuration.
Multi-queue support

Missing Features and Known Issues/Limitations in Driver

The driver assumes that Axi Ethernet IP is connected to the DMA at the hardware level.
The driver doesn't use dma engine framework and contains DMA programming sequence i.e doesn't use separate DMA driver. Hence compatibility string of axidma node (DTS) is set to a dummy device-tree property compatible = "xlnx,eth-dma";
The driver doesn't support software time-stamping. It supports only hardware time-stamping.
PTP synchronization along with high speed traffic (iperf or netperf) is not supported as under heavy load, timestamp in FIFO and DMA data in BD is expected to go out of sync and remain so until the interface is reset.
No support for fixed-link.
For 1588 testing the Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level. For axiethernet 1G/10G subsystem only 2-step PTP is supported.
10G/25G and USXGMII configurations do not support dynamic link status/change in the background as there is no external PHY using PHY framework.
Pause frame solution is not supported and hence there could be RX overruns errors in bidirectional throughput.
The driver supports MCDMA using kernel config i.e CONFIG_AXIENET_HAS_MCDMA option. So in multi-instance scenario driver will only support a single DMA type i.e 1G + MCDMA and 10G + MCDMA.
The driver doesn't support extended multicast and VLAN support. Limited validation of multicast and vlan support.
Runtime Switchable mode.
25G Ethernet Subsystem(PG210).
MRMAC speeds 40G/50G/100G are not supported yet.
MRMAC multi-lane support is not independent because if common GT reset logic exists in subsystem.
On versal support is limited to AXI 1G/2.5G Ethernet subsystem (without PTP) and MRMAC.

Info
NOTE: Relevant missing Features and Known Issues/Limitations in IP:

Multiple TX and RX channel in MCDMA have common configuration and reset registers and hence cannot be used independently by multiple MACs. For ex., if XXV Ethernet instance 1 uses channel 0-4 of MCDMA and then XXV Ethernet instance 2 uses channels 5-15, then resets during driver initialization and error management effect all channels and both instance need to use common registers. Due to this limitation, multiple MACs cannot be used with a single MCDMA.

Important AR links

AXI Ethernet driver in specific MCDMA configuration throws swiotlb full error with jumbo frames. Please refer to 2020.x AR-75128.
Default DTG generation for XXV Ethernet designs fails on 2020.2. Please refer to AR-76029 and AR-76457.

Kernel Configuration

The following config options should be enabled in order to build the Axi Ethernet driver
CONFIG_ETHERNET
CONFIG_NET_VENDOR_XILINX
CONFIG_XILINX_AXI_EMAC
CONFIG_AXIENET_HAS_MCDMA (Select this option In the design if Axi Ethernet is configured with Axi MCDMA)
CONFIG_XILINX_PHY (For testing SGMII/1000Base-x Configuration with PCS/PMA Core)

Image Removed

Device-tree

For more details on phy bindings please refer "Documentation/devicetree/bindings/net/phy.txt"

Code Block

theme	Midnight

axi_ethernet_eth_buf: ethernet@40c00000 {
axistream-connected = <&axi_dma_1>;
axistream-control-connected = <&axi_dma_1>;
clock-frequency = <100000000>;
clocks = <&clk_bus_0>;
compatible = "xlnx,axi-ethernet-1.00.a";
device_type = "network";
interrupt-parent = <&microblaze_1_axi_intc>;
interrupts = <4 2>;
reg = <0x40c00000 0x40000>;
xlnx,phy-type = <0x4>;
xlnx,phyaddr = <0x1>;
xlnx,rxcsum = <0x0>;
xlnx,rxmem = <0x8000>;
xlnx,txcsum = <0x0>;
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@7 {
device_type = "ethernet-phy";
reg = <7>;
};
};
};

Soft Ethernet MAC(1G, legacy 10G or 10G/25G MAC, MRMAC) Configured with MCDMA

When Axi Ethernet (10G/25G MAC) configured with MCDMA device-tree node will be like below
Code Block

theme	Midnight

xxv_ethernet_0: ethernet@80020000 { axistream-connected = <&axi_dma_hier_axi_mcdma_0>; axistream-control-connected = <&axi_dma_hier_axi_mcdma_0>; clock-frequency = <100000000>; clock-names = "rx_core_clk_0", "dclk", "s_axi_aclk_0"; clocks = <&misc_clk_0>, <&clk 72>, <&clk 71>; compatible = "xlnx,xxv-ethernet-2.5", "xlnx,xxv-ethernet-1.0";

Axi Ethernet Linux driver for Microblaze, Zynq, Zynq Ultrascale+ MPSoC and Versal

Introduction

HW IP features

AXI 1G/2.5G Ethernet Subsystem (PG138)

Support for MII, GMII, RGMII, SGMII, and 1000BASE-X PHY interfaces
Support for 1000BASE-X and SGMII over select Input/Output (I/O) low voltage differential signaling (LVDS)
Support for pause frames for flow control
Media Independent Interface Management
Ethernet Audio Video Bridging (AVB) support
AXI4-Stream transmit/receive interface
Support for 2.5G Ethernet
IEEE Standard 1588 Support
AXI4-Lite register interface

10 Gigabit Ethernet subsystem (PG157)

Designed to 10 Gigabit Ethernet specification IEEE Standard 802.3-2012
AXI4-Stream protocol support on client TX and RX interfaces
Configured and monitored through an optional AXI4-Lite Management Data interface or using status and configuration vectors
Supports 10GBASE-SR, -LR and -ER optical links in Zynq-7000, UltraScale™, Virtex-7, and Kintex-7 devices (LAN mode only)
Supports 10GBASE-KR backplane links including Auto-Negotiation (AN), Training and Forward Error Correction (FEC)
Supports Deficit Idle Count
Comprehensive statistics gathering
Supports 802.3 and 802.1Qbb flow control
Supports VLAN and jumbo frames
Custom Preamble mode
Independent TX and RX Maximum Transmission Unit (MTU) frame length
Supports high accuracy IEEE Standard 1588-2008 1-step and 2-step timestamping on a 10GBASE-R network interface

10G/25G Ethernet Subsystem (PG210)

Designed to the Ethernet requirements for 10/25 Gb/s operation specified by IEEE 802.3 Clause 49, IEEE 802.3by, and the 25G Ethernet Consortium
Includes complete Ethernet MAC and PCS/PMA functions or standalone PCS/PMA for 25Gb/s operation
Includes complete Ethernet MAC and PCS/PMA functions, standalone MAC or standalone PCS/PMA for 10 Gb/s operation
Simple packet-oriented user interface
Comprehensive statistics gathering
Status signals for all major functional indicators
BASE-R PCS sublayer operating at 10.3125Gb/s or 25.78125Gb/s
Optional clause 74 BASE-KR FEC sublayer
Optional Auto-Negotiation
Optional clause 108 25G Reed-Solomon Forward Error Correction (RS-FEC) sublayer
Custom Preamble mode
Optional IEEE 1588 1-step and 2-step timestamping
Runtime switchable between 10G and 25G

USXGMII Ethernet Subsystem (PG251)

Designed to meet the USXGMII specification EDCS-1467841 revision 1.4
Supports 10M, 100M, 1G, 2.5G, 5G, or 10GE data rates over a 10.3125 Gb/s link
Both media access control (MAC) and PCS/PMA functions are included
Code replication/removal of lower rates onto the 10GE link
Rate adaption onto user clock domain
Low data path latency
32-bit AXI4-Stream interface for datapath
Optional AXI4-Lite register interface
Support for 802.3x and priority-based pause operation
Detailed statistics gathering
Support for custom preambles
Supports deficit idle count (DIC)

MRMAC Ethernet Subsystem (PG314)

Hardened Ethernet IP block on Versal.
Multi rate Ethernet MAC supporting speeds from 10G to 100G.
- The driver supports 25GE and 10GE with 1 to 4 lanes.
Hardened IP (to be used with Soft DMA and logic for driver subsystems)
High performance, low latency.
Low data path latency
User-side AXI4-Stream interface for data
AXI4-Lite register interface
Detailed statistics gathering
IEEE1588 support

Switchable 1/10/25G IP support (PG292)

Designed to the Ethernet requirements for 1/10 Gb/s operation specified by IEEE 802.3 Clause 49 or Clause 36
Runtime switchable Ethernet MAC and PCS/ PMA functions for 1/10/25 Gb/s operation.
Supports only GTHE3/GTYE3 and GTHE4/GTYE4 transceiver supported devices
Include Auto Negotiation (Clause-73)
Enable Link Training (Clause 72)

Features supported in the driver

Support ethernet IPs- AXI 1G/2.5G Ethernet subsystem (PG138), 10G Ethernet subsystem(PG157), 10G Ethernet Subsystem(PG210), USXGMII(PG251), MRMAC, Switchable 1/10/25G.
IEEE 1588 Support for 1G and legacy 10G MAC (PG157), 10G Ethernet subsystem and 25G Ethernet subsystem (PG210) and MRMAC
Speed support for 10/100/1000 Mbps for 1G MAC
10G Base-R support for Legacy 10G MAC(PG157) and 10G MAC (PG210)
10G and 25G speed support for MRMAC
Support for GMII/RGMII/SGMII/1000Base-X Phy Configurations
Supports Independent 4K, 8K, 16K, or 32KB TX and RX frame buffer memory
Support for common ethtool queries.
NAPI support.
Full/Partial Checksum offload support
Support for Jumbo Frames
Supports AXI DMA and AXI MCDMA dma configuration.
Multi-queue support
Switchable 1/10/25G IP supports 1G or 10G runtime switchable speeds in the driver. It will switch automatically based on the host configuration.

Missing Features and Known Issues/Limitations in Driver

The driver assumes that Axi Ethernet IP is connected to the DMA at the hardware level.
The driver doesn't use dma engine framework and contains DMA programming sequence i.e doesn't use separate DMA driver. Hence compatibility string of axidma node (DTS) is set to a dummy device-tree property compatible = "xlnx,eth-dma";
The driver doesn't support software time-stamping. It supports only hardware time-stamping.
PTP synchronization along with high speed traffic (iperf or netperf) is not supported as under heavy load, timestamp in FIFO and DMA data in BD is expected to go out of sync and remain so until the interface is reset.
- This is a limitation on Soft Ethernet designs which have HW timestamp FIFOs. This issue is not relevant to designs with inline HW timestamping.
No support for fixed-link.
For 1588 testing the Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level. For axiethernet 1G/10G subsystem only 2-step PTP is supported.
10G/25G and USXGMII configurations do not support dynamic link status/change in the background as there is no external PHY using PHY framework.
Pause frame solution is not supported and hence there could be RX overruns errors in bidirectional throughput.
The driver supports MCDMA using kernel config i.e CONFIG_AXIENET_HAS_MCDMA option. So in multi-instance scenario driver will only support a single DMA type i.e 1G + MCDMA and 10G + MCDMA.
The driver doesn't support extended multicast and VLAN support. Limited validation of multicast and vlan support.
Runtime Switchable mode.
MRMAC speeds 40G/50G/100G are not supported yet.
MRMAC multi-lane support is not independent because if common GT reset logic exists in subsystem.
On versal support is limited to AXI 1G Ethernet subsystem (without PTP, 2.5G support), XXV Ethernet subsystem (without PTP, validated at 25G) and MRMAC.
Switchable 1/10/25G IP support is only validated at 1G and 10G on Zynq Ultrascale+ MPSoC

Info
NOTE: Relevant missing Features and Known Issues/Limitations in IP:

Multiple TX and RX channel in MCDMA have common configuration and reset registers and hence cannot be used independently by multiple MACs. For ex., if XXV Ethernet instance 1 uses channel 0-4 of MCDMA and then XXV Ethernet instance 2 uses channels 5-15, then resets during driver initialization and error management effect all channels and both instance need to use common registers. Due to this limitation, multiple MACs cannot be used with a single MCDMA.
Switchable 1/10/25G IP currently does not support dynamic switch for 25G. Will implement in future.

Important AR links

AXI Ethernet driver in specific MCDMA configuration throws swiotlb full error with jumbo frames. Please refer to 2020.x AR-75128.
Default DTG generation for XXV Ethernet designs fails on 2020.2. Please refer to AR-76029 and AR-76457.

Kernel Configuration

The following config options should be enabled in order to build the Axi Ethernet driver
CONFIG_ETHERNET
CONFIG_NET_VENDOR_XILINX
CONFIG_XILINX_AXI_EMAC
CONFIG_AXIENET_HAS_MCDMA (Select this option In the design if Axi Ethernet is configured with Axi MCDMA)
CONFIG_XILINX_PHY (For testing SGMII/1000Base-x Configuration with PCS/PMA Core)

Image Added

Device-tree

For more details on phy bindings please refer "Documentation/devicetree/bindings/net/phy.txt"

Code Block

theme	Midnight

axi_ethernet_eth_buf: ethernet@40c00000 {
axistream-connected = <&axi_dma_1>;
axistream-control-connected = <&axi_dma_1>;
clock-frequency = <100000000>;
clocks = <&clk_bus_0>;
compatible = "xlnx,axi-ethernet-1.00.a";
device_type = "network";
	local-mac-addressinterrupt-parent = <&microblaze_1_axi_intc>;
interrupts = [00<4 0a2>;
35reg 00= 00<0x40c00000 00]0x40000>;
	xlnx,phy-modetype = "base-r"<0x4>;
	regxlnx,phyaddr = <0x0 0x80020000 0x0 0x10000>;
	xlnx<0x1>;
xlnx,rxcsum = <0x0>;
xlnx,rxmem = <0x0><0x8000>;
	xlnx,add-gt-cntrl-sts-portstxcsum = <0x0>;
	xlnx,anlt-clk-in-mhzphy-handle = <0x64><&phy0>;
	xlnx,axis-tdata-width
mdio {
#address-cells = <0x40><1>;
	xlnx,axis-tkeep-width#size-cells = <0x7>;
	xlnx,base-r-kr<0>;
phy0: phy@7 {
device_type = "BASEethernet-Rphy";
	xlnx,channel-idsreg = "1","2","3","4","5","6","7","8","9","a","b","c","d","e","f","10";
	xlnx,clocking = "Asynchronous";
	xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";
	xlnx,data-path-interface = "AXI Stream";
	xlnx,enable-datapath-parity = <0x0>;
	xlnx,enable-pipeline-reg = <0x0>;
	xlnx,enable-preemption = <0x0>;
	xlnx,enable-preemption-fifo = <0x0>;
	xlnx,enable-rx-flow-control-logic = <0x0>;
	xlnx,enable-time-stamping = <0x1>;
	xlnx,enable-tx-flow-control-logic = <0x0>;
	xlnx,enable-vlane-adjust-mode = <0x0>;
	xlnx,family-chk = "zynquplus";
	xlnx,fast-sim-mode = <0x0>;
	xlnx,gt-diffctrl-width = <0x4>;
	xlnx,gt-drp-clk = "100.00";
	xlnx,gt-group-select = "Quad X0Y0";
	xlnx,gt-location = <0x1>;
	xlnx,gt-ref-clk-freq = "156.25";
	xlnx,gt-type = "GTH";
	xlnx,include-auto-neg-lt-logic = "None";
	xlnx,include-axi4-interface = <0x1>;
	xlnx,include-fec-logic = <0x0>;
	xlnx,include-rsfec-logic = <0x0>;
	xlnx,include-shared-logic = <0x1>;
	xlnx,include-user-fifo = <0x1>;
	xlnx,lane1-gt-loc = "X0Y4";
	xlnx,lane2-gt-loc = "NA";
	xlnx,lane3-gt-loc = "NA";
	xlnx,lane4-gt-loc = "NA";
	xlnx,line-rate = <0xa>;
	xlnx,mii-ctrl-width = <0x4>;
	xlnx,mii-data-width = <0x20>;
	xlnx,num-of-cores = <0x1>;
	xlnx,num-queues = /bits/ 16 <0x10>;
	xlnx,ptp-clocking-mode = <0x0>;
	xlnx,ptp-operation-mode = <0x2>;
	xlnx,runtime-switch = <0x0>;
	xlnx,rxmem = <0x40000>;
	xlnx,switch-1-10-25g = <0x0>;
	xlnx,tx-latency-adjust = <0x0>;
	xlnx,tx-total-bytes-width = <0x4>;
	xlnx,xgmii-interface = <0x1>;
	interrupt-names = "mm2s_ch1_introut", "mm2s_ch2_introut", "mm2s_ch3_introut", "mm2s_ch4_introut", "mm2s_ch5_introut", "mm2s_ch6_introut", "mm2s_ch7_introut", "mm2s_ch8_introut", "mm2s_ch9_introut", "mm2s_ch10_introut", "mm2s_ch11_introut", "mm2s_ch12_introut", "mm2s_ch13_introut", "mm2s_ch14_introut", "mm2s_ch15_introut", "mm2s_ch16_introut", "s2mm_ch1_introut", "s2mm_ch2_introut", "s2mm_ch3_introut", "s2mm_ch4_introut", "s2mm_ch5_introut", "s2mm_ch6_introut", "s2mm_ch7_introut", "s2mm_ch8_introut", "s2mm_ch9_introut", "s2mm_ch10_introut", "s2mm_ch11_introut", "s2mm_ch12_introut", "s2mm_ch13_introut", "s2mm_ch14_introut", "s2mm_ch15_introut", "s2mm_ch16_introut";
	interrupt-parent = <&gic>;
	interrupts = <0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 <7>;
};
};
};

Soft Ethernet MAC(1G, legacy 10G or 10G/25G MAC, MRMAC) Configured with MCDMA

When Axi Ethernet (10G/25G MAC) configured with MCDMA device-tree node will be like below

Code Block

theme	Midnight

 xxv_ethernet_0: ethernet@80020000 {
	axistream-connected = <&axi_dma_hier_axi_mcdma_0>;
	axistream-control-connected = <&axi_dma_hier_axi_mcdma_0>;
	clock-frequency = <100000000>;
	clock-names = "rx_core_clk_0", "dclk", "s_axi_aclk_0";
	clocks = <&misc_clk_0>, <&clk 72>, <&clk 71>;
	compatible = "xlnx,xxv-ethernet-2.5", "xlnx,xxv-ethernet-1.0";
	device_type = "network";
	local-mac-address = [00 0a 35 00 00 00];
	phy-mode = "base-r";
	reg = <0x0 0x80020000 0x0 0x10000>;
	xlnx = <0x0>;
	xlnx,add-gt-cntrl-sts-ports = <0x0>;
	xlnx,anlt-clk-in-mhz = <0x64>;
	xlnx,axis-tdata-width = <0x40>;
	xlnx,axis-tkeep-width = <0x7>;
	xlnx,base-r-kr = "BASE-R";
	xlnx,channel-ids = "1","2","3","4","5","6","7","8","9","a","b","c","d","e","f","10";
	xlnx,clocking = "Asynchronous";
	xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";
	xlnx,data-path-interface = "AXI Stream";
	xlnx,enable-datapath-parity = <0x0>;
	xlnx,enable-pipeline-reg = <0x0>;
	xlnx,enable-preemption = <0x0>;
	xlnx,enable-preemption-fifo = <0x0>;
	xlnx,enable-rx-flow-control-logic = <0x0>;
	xlnx,enable-time-stamping = <0x1>;
	xlnx,enable-tx-flow-control-logic = <0x0>;
	xlnx,enable-vlane-adjust-mode = <0x0>;
	xlnx,family-chk = "zynquplus";
	xlnx,fast-sim-mode = <0x0>;
	xlnx,gt-diffctrl-width = <0x4>;
	xlnx,gt-drp-clk = "100.00";
	xlnx,gt-group-select = "Quad X0Y0";
	xlnx,gt-location = <0x1>;
	xlnx,gt-ref-clk-freq = "156.25";
	xlnx,gt-type = "GTH";
	xlnx,include-auto-neg-lt-logic = "None";
	xlnx,include-axi4-interface = <0x1>;
	xlnx,include-fec-logic = <0x0>;
	xlnx,include-rsfec-logic = <0x0>;
	xlnx,include-shared-logic = <0x1>;
	xlnx,include-user-fifo = <0x1>;
	xlnx,lane1-gt-loc = "X0Y4";
	xlnx,lane2-gt-loc = "NA";
	xlnx,lane3-gt-loc = "NA";
	xlnx,lane4-gt-loc = "NA";
	xlnx,line-rate = <0xa>;
	xlnx,mii-ctrl-width = <0x4>;
	xlnx,mii-data-width = <0x20>;
	xlnx,num-of-cores = <0x1>;
	xlnx,num-queues = /bits/ 16 <0x10>;
	xlnx,ptp-clocking-mode = <0x0>;
	xlnx,ptp-operation-mode = <0x2>;
	xlnx,runtime-switch = <0x0>;
	xlnx,rxmem = <0x40000>;
	xlnx,switch-1-10-25g = <0x0>;
	xlnx,tx-latency-adjust = <0x0>;
	xlnx,tx-total-bytes-width = <0x4>;
	xlnx,xgmii-interface = <0x1>;
	interrupt-names = "mm2s_ch1_introut", "mm2s_ch2_introut", "mm2s_ch3_introut", "mm2s_ch4_introut", "mm2s_ch5_introut", "mm2s_ch6_introut", "mm2s_ch7_introut", "mm2s_ch8_introut", "mm2s_ch9_introut", "mm2s_ch10_introut", "mm2s_ch11_introut", "mm2s_ch12_introut", "mm2s_ch13_introut", "mm2s_ch14_introut", "mm2s_ch15_introut", "mm2s_ch16_introut", "s2mm_ch1_introut", "s2mm_ch2_introut", "s2mm_ch3_introut", "s2mm_ch4_introut", "s2mm_ch5_introut", "s2mm_ch6_introut", "s2mm_ch7_introut", "s2mm_ch8_introut", "s2mm_ch9_introut", "s2mm_ch10_introut", "s2mm_ch11_introut", "s2mm_ch12_introut", "s2mm_ch13_introut", "s2mm_ch14_introut", "s2mm_ch15_introut", "s2mm_ch16_introut";
	interrupt-parent = <&gic>;
	interrupts = <0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 89 4 0 90 4 0 90 4 0 90 4>;4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4 0 90 4>;

	xxv_ethernet_0_mdio: mdio {
			#address-cells = <1>;
			#size-cells = <0>;
	};
};

...

The driver supports channel observer feature through sysfs. This custom feature is useful in multi-core (Observer) system where MCDMA is a shared resource for all cores. MCDMA IP supports a maximum of six cores and 16 Channels can be distributed across each core as a static configuration. The Channel Observer is available for each group and provides the status about the channels in a group being serviced.
The driver supports per channel weight configuration through sysfs. This custom feature specifies the channel weight i.e number of packets to be sent in one iteration.
The driver supports Linux multiqueue networking. It uses the alloc_etherdev_mq() function to allocate the subqueues for the device.
The userspace command 'tc,' part of the iproute2 package, is used to configure qdiscs. To add the MULTIQ qdisc assuming the device is called eth0, run the following command:
# tc qdisc add dev eth0 root handle 1: multiq
The qdisc will allocate the number of bands to equal the number of queues that the device reports, and bring the qdisc online.
Assuming eth0 has 4 Tx queues, the band mapping would look like:
band 0 => queue 0
band 1 => queue 1
band 2 => queue 2
band 3 => queue 3

...

To support USXGMII + MCDMA, use above devicetree as reference and select:
xlnx,phy-type = <0x7>;

Related device tree information

For PHY related DT information, refer to

https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/ethernet-phy.txtyaml

When selecting phy specific settings, make sure to mention interface type, speed (if limited/fixed) and phy address properties.
PHY/Converter devices that may be used with this MAC:
-> Xilinx GMII2RGMII converter (https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt)
-> Xilinx PCS PMA PHY

IEEE 1588 Support

The Existing Axi Ethernet driver in the Xilinx git hub supports 1588 for 1G MAC and legacy 10G MAC and 10G/25G MAC
It does timestamp at the MAC level. 1588 is supported in 7-series and Zynq.
The Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level.

Note:
In order to test the hardware platform, a 1588 timestamp capable timer is required at the h/w level.

Prerequisite for 1588 testing:
Need to enable XILINX_AXI_EMAC_HWTSTAMP in the kernel config which does the timestamping at the MAC level (Tx/Rx)
Users should write their own timer driver for time stamping which does time adjustment/ freq adjustment.

For testing 1588 please refer to Testing tools section below.

1588 Device-tree Example Node

Code Block

theme	Midnight

     axi_ethernet_eth_buf: ethernet@40c00000 {     axi_ethernet_eth_buf: ethernet@40c00000 {
            axistream-connected = <&axi_dma_1>;
            axififo-connected = <&axi_fifo_0>;
            clock-frequency = <100000000>;
            clocks = <&clk_bus_0>;
            compatible = "xlnx,axi-ethernet-1.00.a";
            device_type = "network";
            interrupt-parent = <&microblaze_1_axi_intc>;
            interrupts = <4 2>;
            reg = <0x40c00000 0x40000>;
            xlnx,phy-type = <0x4>;
            xlnx,phyaddr = <0x1>;
            xlnx,rxcsum = <0x0>;
            xlnx,rxmem = <0x8000>;
            xlnx,txcsum = <0x0>;
            xlnx,txmem = <0x8000>;
            phy-handle = <&phy0>;
            mdio {
              #address-cells = <1>;
              #size-cells = <0>;
                  phy0: phy@7 {
                      compatible = "marvell,88e1111";
                     device_type = "ethernet-phy";
                     reg = <7>;
                };
            };
        };

MRMAC 1588 support is tested with Xilinx 1588 Timer-Syncer block details of which can be found here:

https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/ptp/ptp-xilinx.yaml

https://github.com/Xilinx/linux-xlnx/blob/master/drivers/ptp/ptp_xilinx.c

SWITCHABLE 1/10/25G IP

When Axi Ethernet (1G/10G/25G MAC) is configured with DMA device-tree node will be like below

Code Block

             axi_dma1: dma@80000000 {                                                  
                        #dma-cells = <0x01>;                                    
                        clock-names = "s_axi_lite_aclk\0m_axi_sg_aclk\0m_axi_mm2s_aclk\0m_axi_s2mm_aclk";
                        clocks = <0x03 0x47 0x03 0x47 0x3b 0x3b>;               
                        compatible = "not";                                     
                        interrupt-names = "mm2s_introut", "s2mm_introut";         
                        interrupt-parent = <0x04>;                              
                        interrupts = <0x00 0x59 0x04 0x00 0x5a 0x04>;           
                        reg = <0x00 0x80000000 0x00 0x10000>;                   
                        xlnx,addrwidth = [20];                                  
                        xlnx,include-sg;                                        
                        xlnx,sg-length-width = <0x10>;                          
                        status = "disabled";
						xlnx,include-dre;                                    
                        phandle = <0xac>;                                       
                                                                                
                        dma-channel@80000000 {                                  
                                compatible = "xlnx,axi-dma-mm2s-channel";       
                                dma-channels = <0x01>;                          
                                interrupts = <0x00 0x59 0x04>;                  
                                xlnx,datawidth = <0x40>;                        
                                xlnx,device-id = <0x00>;                        
                                xlnx,include-dre;                               
                        };                                                      
                                                                                
                        dma-channel@80000030 {                                  
                                compatible = "xlnx,axi-dma-s2mm-channel";       
                                dma-channels = <0x01>;                          
                                interrupts = <0x00 0x5a 0x04>;                  
                                xlnx,datawidth = <0x40>;                        
                                xlnx,device-id = <0x00>;                        
                                xlnx,include-dre;                               
                        };                                                      
                };

               ethernet_1_10_25g@80010000 {                                    
                        clock-names = "rx_core_clk_0", "rx_core_clk_1", "dclk", "s_axi_aclk_0", "s_axi_aclk_1";
                        clocks = <0x3b 0x3b 0x03 0x48 0x03 0x47 0x03 0x47>;         
                        compatible = "xlnx,ethernet-1-10-25g-2.7";              
                        reg = <0x00 0x80010000 0x00 0x10000>;                   
                        xlnx,add-gt-cntrl-sts-ports = <0x00>;                   
                        xlnx,anlt-clk-in-mhz = <0x4b>;                          
                        xlnx,axis-tdata-width = <0x40>;                         
                        xlnx,axis-tkeep-width = <0x07>;                         
                        xlnx,base-r-kr = "BASE-R";                              
                        xlnx,clocking = "Asynchronous";                         
                        xlnx,core = "Ethernet MAC+PCS/PMA 64-bit";              
                        xlnx,data-path-interface = "AXI Stream";                
                        xlnx,enable-pipeline-reg = <0x00>;                      
                        xlnx,enable-preemption = <0x00>;                        
                        xlnx,enable-rx-flow-control-logic = <0x00>;             
                        xlnx,enable-time-stamping = <0x00>;                     
                        xlnx,enable-tx-flow-control-logic = <0x00>;             
                        xlnx,enable-vlane-adjust-mode = <0x00>;                 
                        xlnx,family-chk = "zynquplus";                          
                        xlnx,fast-sim-mode = <0x00>;                            
                        xlnx,gt-drp-clk = "50.00";                              
                        xlnx,gt-group-select = "Quad X0Y0";                     
                        xlnx,gt-location = <0x01>;                              
                        xlnx,gt-ref-clk-freq = "156.25";                        
                        xlnx,gt-type = "GTH";                                   
                        xlnx,include-auto-neg-lt-logic = "Include AN Logic";    
                        xlnx,include-axi4-interface = <0x01>;                   
                        xlnx,include-fec-logic = <0x00>;                        
                        xlnx,include-lt-logic = "Include LT Logic";             
                        xlnx,include-rsfec-logic = <0x00>;                      
                        xlnx,include-shared-logic = <0x01>;                     
                        xlnx,include-statistics-counters = <0x01>;              
                        xlnx,include-system-timer-syncers = <0x00>;             
                        xlnx,include-user-fifo = <0x00>;                        
                        xlnx,lane1-gt-loc = "X1Y14";                            
                        xlnx,lane2-gt-loc = "X1Y15";                            
                        xlnx,lane3-gt-loc = "NA";                               
                        xlnx,lane4-gt-loc = "NA";                               
                        xlnx,line-rate = <0x0a>;                                
                        xlnx,num-of-cores = <0x02>;                             
                        xlnx,ptp-clocking-mode = <0x00>;                        
                        xlnx,ptp-operation-mode = <0x02>;                       
                        xlnx,runtime-switch = "1G / 10G";                       
                        xlnx,statistics-counters-size = <0x30>;                 
                        xlnx,statistics-regs-type = <0x00>;                     
                        xlnx,timer-format = <0x00>;                             
                        xlnx,tx-latency-adjust = <0x00>;                        
                        xlnx,tx-total-bytes-width = <0x04>;                     
                        xlnx,xgmii-interface = <0x01>;                          
                        axistream-connected = <&axi_

...

dma1>;

...

              
                        axistream-control-connected = <&axi_

...

dma1>;

...

local-mac-address =

...

[00 0a 35 00 00 00];

...

             interrupt-parent =

...

<0x04>;

...

        interrupt-names = "mm2s_introut", "s2mm_introut";

...

interrupts = <0x00 0x59 0x04 0x00 0x5a 0x04>;

...

xlnx,addrwidth =

...

[20];

...

                 phandle =

...

<0xae>;

...

};

...

MRMAC 1588 support is tested with Xilinx 1588 Timer-Syncer block details of which can be found here:

https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/ptp/ptp-xilinx.yaml

...

Performance

These benchmark performance numbers were obtained by connecting Xilinx boards to Linux PCs/server machines (Ubuntu/Red Hat Enterprise).
The tools used are netperf or iperf (Refer to tool information below).

...

NOTE: CPU utilization reported in below performance tables is an aggregate of all CPU's. i.e on ZynqMP platform, it reports combined utilization of all four A53 cores.

1G Ethernet with AXIDMA

Kernel version: 56.101

AXI 1G/2.5G Ethernet Subsystem : TX and RX full checksum offload enabled.

ZynqMP
Board: ZCU102 board (production silicon) + SFP Module

...

NOTE- There is ~10% drop (compared to 2019.2) in performance for 1500 MTU.
The drop is due to enable CONFIG_OPTIMIZE_INLINING forcibly” commit in linux kernel.

Kernel and networking stack is full of inline functions and it could be some unoptimized
inline function (could also be dependent on gcc version) leading to a performance drop.

The performance drop is observed on GEM and Xilinx Axi Ethernet MAC’s on Zynq

The plan is to document the performance drop on zynq and initiate the discussion with
the mainline community so that it is analyzed by respective kernel maintainers.

	TCP (Mbps)				UDP (Mbps)
MTU	TX	CPU(%)	RX	CPU(%)	TX	CPU(%)	RX	CPU(%)
1500	740	67.53	537	89.39	453	52.86	456	88.72
8192	977	60.69	732	50.26	743	36.10	643	50.32

...

Traditionally microblaze designs are not targeted for high performance applications so only functional sanity is done.

10G Ethernet with AXIMCDMA

Kernel version: 56.101

ZynqMP
Board: ZCU102 board (production silicon) + SFP Module

	TCP (Gbps)				UDP (Gbps)
MTU	TX	CPU(%)	RX	CPU(%)	TX	CPU(%)	RX	CPU(%)
1500	2.29	50.91	1.7376	064.9871	3.03	99.93	1.65	70.04
9000	5.0	52.35	3.56	53.9	6.51	65.09	4.63	54.28

NOTE: In this design 1588 is not enabled.

Setup Details
Host setup: Dell System Precision Tower 7910 (0619)
Iperf: iperf 3-CURRENT (cJSON 1.5.2)
OS : Linux 3.13.0-147-generic #196-Ubuntu SMP Wed May 2 15:51:34 UTC 2018 x86_64
NIC (10G Solarflare's SFN6322F Dual-Port 10GbE SFP+ Adapter) : Default

Performance benchmarking

Pre-requisites:

Set Ethernet MCDMA TX interrupt affinity to core-1

root@10g-mcdma-no1588-build:~# echo 2 > /proc/irq/xx/smp_affinity

Run iperf servers on ZynqMP (core2 and core3)

root@10g-mcdma-no1588-build:~# taskset -c 2 2 iperf3 -s -p 5101 &
root@10g-mcdma-no1588-build:~# taskset -c 3 iperf3 -s -p 5102 &

CPU Utilization reporting

root@10g-mcdma-no1588-build:~# ./mpstat -P ALL 1 50

Run iperf servers on the remote host

server:~# iperf3 -s -p 5101 & ; iperf3 -s -p 5102 & ; iperf3 -s -p 5103 & ; iperf3 -s -p 5101 5104 &
root@10g-mcdma-no1588-build:~# taskset -c 3 iperf3 -s -p 5102 &

CPU Utilization reporting

root@10g-mcdma-no1588-build:~# ./mpstat -P ALL 1 50

Run iperf servers on the remote host

server:~# iperf3 -s -p 5101 & ; iperf3 -s -p 5102 & ; iperf3 -s -p 5103 & ; iperf3 -s -p 5104 &
Steps:

View file

name	10G_MCDMA_bencmarking_steps_2019.txt
height	250

Test Procedure

Diagnostic and Protocol Tests

PING
This utility used to test the reachability of a host on an Internet Protocol(IP) network and to measure the round trip time for messages sent from the originating host to a destination computer
How to Run
ping <Remote IP Address>
Telnet
telnet <Server IP Address>
Pkt Generator
Please refer the below link for how to run and various options
https://www.kernel.org/doc/Documentation/networking/pktgen.txt

Stress Test

Iperf with option -d
Run iperf in dual testing mode. This will cause the server to connect back to the client on the port specified in the -L option (or defaults to the port the client connected to the server on). This is done immediately therefore running the tests simultaneously.
./iperf -c <Server IP> -d
Ping flood test
Users can send hundred or more packets per second using -f option. It prints a ‘.’ when a packet is sent, and a backspace is printed when a packet is received

Code Block

theme	Midnight

ping -f localhost

Performance Test

Netperf
More information please refer to the below link
http://www.netperf.org/netperf/
How to Run
Server:
netserver
Client:
taskset 2 ./netperf -H <Server IP> -t TCP_STREAM
taskset 2 ./netperf -H <Server IP> -t UDP_STREAM
Iperf
More information please refer to the below link
http://en.wikipedia.org/wiki/Iperf
How to Run
Server:
./iperf -s -u
./iperf -s
Client:
./iperf -c <Server IP> -u -b <bandwidth>
./iperf -c <Server IP>

1588 Testing

ptp4l implements the PTP boundary clock and ordinary clock. When hardware time stamping is enabled, ptp4l synchronizes the PTP hardware clock to the master clock. With software time stamping, it synchronizes the system clock to the master clock. phc2sys is needed only with hardware time stamping to synchronize the system clock to the PTP hardware clock on the network interface card (NIC).

Build Instructions for ptp4l application

Get the source

     git clone http://git.code.sf.net/p/linuxptp/code linuxptp

Set the CROSS_COMPILE environment variable arm toolchain
Install the kernel headers

https://www.kernel.org/doc/Documentation/kbuild/headers_install.txt

Include the headers path in makefile

INC = -I/proj/epdsw/punnaiah/git/test/ethernet/1588/header/include
CFLAGS = -Wall $(VER) $(incdefs) $(DEBUG) $(INC) $(EXTRA_CFLAGS)

run make

Execution steps

In order to perform master-slave sync, run the following:

Master (linux server) : ptp4l -i < interface name> -m
Slave (xilinx board) : ptp4l -i <interface name> -m -s

NOTE: If intended before synchronization phc2sys -s <devicename> -w & can be run to synchronize the system clock to a PTP hardware clock.

Image Removed

Synchronization is stabilized in a few secs.

Image Removed

...

The current Axi Ethernet driver is currently in sync with mainline except for the following

SGMII/1000Base-x support
NAPI Support
Support for 1588
Support for legacy 10G MAC
Support for 1G MAC Non-processor Mode
Support for 10G/25G MAC with 1588
Support for 2.5G MAC with 1588
Support for Axi Ethernet with AXI MCDMA Configuration
Support for USXGMII IP.
Support for MRMAC IP.

Change Log

...

Steps:

View file

name	10G_MCDMA_bencmarking_steps_2019.txt
height	250

Test Procedure

Diagnostic and Protocol Tests

PING
This utility used to test the reachability of a host on an Internet Protocol(IP) network and to measure the round trip time for messages sent from the originating host to a destination computer

How to Run
ping <Remote IP Address>

Telnet
telnet <Server IP Address>

Pkt Generator
Please refer the below link for how to run and various options
https://www.kernel.org/doc/Documentation/networking/pktgen.txt

Stress Test

Iperf with option -d
Run iperf in dual testing mode. This will cause the server to connect back to the client on the port specified in the -L option (or defaults to the port the client connected to the server on). This is done immediately therefore running the tests simultaneously.

./iperf -c <Server IP> -d

Ping flood test
Users can send hundred or more packets per second using -f option. It prints a ‘.’ when a packet is sent, and a backspace is printed when a packet is received

Code Block

theme	Midnight

ping -f localhost

Performance Test

Netperf
More information please refer to the below link
http://www.netperf.org/netperf/

How to Run
Server:
netserver

Client:
taskset 2 ./netperf -H <Server IP> -t TCP_STREAM
taskset 2 ./netperf -H <Server IP> -t UDP_STREAM

Iperf
More information please refer to the below link
http://en.wikipedia.org/wiki/Iperf

How to Run
Server:
./iperf -s -u
./iperf -s

Client:
./iperf -c <Server IP> -u -b <bandwidth>
./iperf -c <Server IP>

1588 Testing

ptp4l implements the PTP boundary clock and ordinary clock. When hardware time stamping is enabled, ptp4l synchronizes the PTP hardware clock to the master clock. phc2sys can be used to synchronize the system clock to the PTP hardware clock on the network interface card (NIC).

Build Instructions for ptp4l application

Get the source

     git clone http://git.code.sf.net/p/linuxptp/code linuxptp

Set the CROSS_COMPILE environment variable arm toolchain
Install the kernel headers

https://www.kernel.org/doc/Documentation/kbuild/headers_install.txt

Include the headers path in makefile

INC = -I/proj/epdsw/punnaiah/git/test/ethernet/1588/header/include
CFLAGS = -Wall $(VER) $(incdefs) $(DEBUG) $(INC) $(EXTRA_CFLAGS)

run make

Execution steps

In order to perform master-slave sync, run the following:

Master (linux server) : ptp4l -i < interface name> -m
Slave (xilinx board) : ptp4l -i <interface name> -m -s

NOTE: If intended before synchronization phc2sys -s <devicename> -w & can be run to synchronize the system clock to a PTP hardware clock.

Image Added

Synchronization is stabilized in a few secs.

Image Added

Mainline status

The current Axi Ethernet driver is not in sync with mainline. The following components need to be upstreamed:

SGMII/1000Base-x support (will be in sync with phylink as per 5.17)
NAPI Support
Support for 1588
Support for legacy 10G MAC
Support for 1G MAC Non-processor Mode
Support for 10G/25G MAC with 1588
Support for 2.5G MAC with 1588
Support for Axi Ethernet with AXI MCDMA Configuration
Support for USXGMII IP.
Support for MRMAC IP.

Change Log

2023.2

Acquire ptp device information dynamically
Add switchable 1/10/25G MAC support
Implement work queue to enable/disable link training.

Commits

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2023.2/drivers/net/ethernet/xilinx

2023.1

6.1 kernel rebase
Added phylink support

Commits:

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2023.1/drivers/net/ethernet/xilinx

2022.2

Bugfix on TX TS FIFO read sequence
Upstream fixes for RX ring refill allocation failure handling and removing dependency on phy-node for axienet_mdio_setup function call
Minor fixes on code indentation and mixed declarations.

2022.1

5.15 kernel rebase
MRMAC bugfix to reporting correct link status at 10G/25G.
XXV bugfix to check for new IP register reporting clock stability.
Bugfixes for DMA error path handling.
Minor cleanup for documentation and GCC warnings.
Note: TSN driver support moved to staging - no effect on any of the Ethernet components discussed in this page.

https://github.com/Xilinx/linux-xlnx/commits/xilinx-v2022.1/drivers/net/ethernet/xilinx

2021.2

Correct phy-mode handling and pass correct mode to PHY framework.
Fix MCMDA crash due to dma map and memory errors by handling the same.
Emaclite bug fixes

...

33ebfdb net: xilinx: axiethernet: Fix crash in ifconfig down
f5b9e58 net: xilinx: axiethernet: Fix axiethernet register description
e491e78 net: xilinx: axiethernet: Check for queue full in transmit path
0ba2b93 net: xilinx: axiethernet: Fix code checker warnings
d4c6c09 net: xilinx: axiethernet: Use %pa format specifier for phys_addr_t type
270968c net: xilinx: axiethernet: Add 64-bit support
d139077 net: xilinx: axiethernet: Extend clocking support
fdce589 net: xilinx: axiethernet: Fix kernel crash on MII ioctl
3f2d6cd net: xilinx: axiethernet: use channel-id for mcdma interrupt names
aaad9c0 net: xilinx: axiethernet: Fix netconsole implementation

2018.3

Sync kconfig description.
In axienet_skb_tstsmp() failure return TX_BUSY.
Add error output on DMA allocation failed.
Fix memory leak in axienet bd_free().
Refactor and split axidma and mcdma programming in separate sources.
Fix dma name buffer size and skb_free in xmit.
Format XXV error output.
Fix compiler warnings.

...

Page Comparison

Versions Compared

Old Version 74

New Version Current

Key

Table of Contents

HW IP features

AXI 1G/2.5G Ethernet Subsystem (PG138)

10 Gigabit Ethernet subsystem (PG157)

10G/25G Ethernet Subsystem (PG210)

USXGMII Ethernet Subsystem (PG251)

MRMAC Ethernet Subsystem (PG251)

Features supported in the driver

Missing Features and Known Issues/Limitations in Driver

Important AR links

Kernel Configuration

Device-tree

Soft Ethernet MAC(1G, legacy 10G or 10G/25G MAC, MRMAC) Configured with MCDMA

Table of Contents

HW IP features

AXI 1G/2.5G Ethernet Subsystem (PG138)

10 Gigabit Ethernet subsystem (PG157)

10G/25G Ethernet Subsystem (PG210)

USXGMII Ethernet Subsystem (PG251)

MRMAC Ethernet Subsystem (PG314)

Switchable 1/10/25G IP support (PG292)

Features supported in the driver

Missing Features and Known Issues/Limitations in Driver

Important AR links

Kernel Configuration

Device-tree

Soft Ethernet MAC(1G, legacy 10G or 10G/25G MAC, MRMAC) Configured with MCDMA

Related device tree information

IEEE 1588 Support

SWITCHABLE 1/10/25G IP

Performance

1G Ethernet with AXIDMA

10G Ethernet with AXIMCDMA

Diagnostic and Protocol Tests

Stress Test

Performance Test

1588 Testing

Change Log

Diagnostic and Protocol Tests

Stress Test

Performance Test

1588 Testing

Mainline status

Change Log