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Tutorial: Modules 1-5 of Introduction to NoC DDRMC Design Flow
Blog: Basic read/write to AXI BRAM from PS-APU through NoC in Versal
CEDStore: AXI DMA on VCK190
Tutorial: Versal Embedded Design, section on Versal ACAP CIPS and NoC (DDR) IP Core Configuration
CEDStore: VCK190/VMK190 Configurable Example Design in Vivado
CEDStore: Simulating with the CIPS Verification IP
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This user brings together the ACAP hardware, board design and software and needs system level debug tools to diagnose and resolve performance and power issues.
Related Links
Tutorial: Versal Embedded Design, section on Debugging Using the Vitis Software Platform
Tutorial: Versal JTAG Boot Tutorial
Chapter 7: Boot and Configuration and Chapter 8: Platform Loader and Manager in UG1304
Blog: How to leverage Versal CIPS IP from MicroBlaze
This post shows how to route a configuration complete signal from the PMC to the PL.
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This user cares about system software interactions with the NoC and DDR MC. This typically occurs during error reporting and handling.
Related Links
AI Engine Development
This user tends not to care about the NoC and DDR MC.
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