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Performance through the HP ports is very dependent on the traffic patterns generated by the PL masters as well as non-deterministic traffic patterns driven by software running on the processors. Both sets of masters will be competing for DDR access. The non-deterministic nature of software running on the processors makes it difficult to model and predict high DDR efficiency. However, you may be able to tweak the default configurations to help meet your system performance requirements. This is not an exhaustive list of the available controls, but the most effective knobs to help shape the HP traffic. The data path from the HP ports in the PL to the DDR memory controller is shown below.

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This article does NOT address:

1. HPC, HPM, ACE, ACP or LPD ports

2. CCI/QVN enablement

3. Impact of SMMU enablement

HP to DDR Data Path

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PS-PL Interface

The PS-PL interface is comprised of an AXI FIFO interface (AFI) per port to bridge the PS and PL domains. The main controls here are the QoS and the issuing capability per port. The QoS specifies the priority of the transaction which is also used to map the channel into traffic classes in the DDR memory controller. The QoS may be static or dynamic depending on your system needs. The issuing capability defines how many HP outstanding transactions may be in-flight at a given time.

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MAX = 533 MTps (8528 MBps)

TPSTps_avg = 0.1 * 533M = 53.3 MTps (852.8 MBps)

TPSTps_max = 0.15 * 533M = 79.95 MTps (1279.2 MBps)

Rate_avg = floor (256 / (100 * BL / %BW_avg)) = floor (4096 / (100 * 16 / 1510)) = 38 25 (0x260x19)

Rate_peak = floor (4096 / (100 * BL / %BW_peak)) = floor (256 / (100 * 16 / 1015)) = 1 2 (0x10x2)

Burstiness = 4

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Outstanding transaction regulation

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APM monitor software running on the RPU echos the data measured from each hard APM to a terminal. Running a monitor on the RPU from OCM allows us to take snapshots of the DDR traffic when running a high level OS like Linux on the APU. Since there is no dependency on the DDR memory, the monitor software will not get blocked from executing no matter how heavy the HP traffic. An advantage of this approach is it does not require JTAG to read the APM registers which can be affected by very high traffic.

Conclusions

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Related Links

1. Zynq UltraScale+ Devices Register Reference

2. Zynq UltraScale+ Device Technical Reference Manual (UG1085)

3. ARM® CoreLink™ NIC-400 Network Interconnect

4. ARM® CoreLink™ QoS-400 Network Interconnect Advanced Quality of Service

5. Quality of Service (QoS) in ARM Systems: An Overview, Ashley Stevens, July 2014

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