Introduction
The gigabit Ethernet controller (GEM) implements a 10/100/1000 Mb/s Ethernet MAC that is compatible with the IEEE Standard for Ethernet (IEEE Std 802.3-2008) and capable of
operating in either half or full-duplex mode in 10/100 mode and full-duplex in 1000 mode. The processing system (PS) is equipped with four gigabit Ethernet controllers. Each
controller can be configured independently. Each controller uses a reduced gigabit media independent interface (RGMII) v2.0 (to save pins).
U-Boot Config
For ZynqMP:
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CONFIG_ZYNQ_GEM=y
CONFIG_DM_ETH=y
CONFIG_NET_RANDOM_ETHADDR=y
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For Zynq
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CONFIG_ZYNQ_GEM=y
CONFIG_NET_RANDOM_ETHADDR=y
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Device Tree
For ZynqMP
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&&gem3 {
status = "okay";
phy-handle = <&&phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&&pinctrl_gem3_default>;
phy0: phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,rxctrl-strap-worka;
};
};
pinctrl_gem3_default: gem3-default {
mux {
function = "ethernet3";
groups = "ethernet3_0_grp";
};
conf {
groups = "ethernet3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74","MIO75";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68","MIO69";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio3";
groups = "mdio3_0_grp";
};
conf-mdio {
groups = "mdio3_0_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
bias-disable;
};
}; |
For Zynq
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&&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ðernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&&pinctrl_gem0_default>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
device_type = "ethernet-phy";
};
};
pinctrl_gem0_default: gem0-default {
mux {
function = "ethernet0";
groups = "ethernet0_0_grp";
};
conf {
groups = "ethernet0_0_grp";
slew-rate = <0>;
io-standard = <4>;
};
conf-rx {
pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
low-power-enable;
bias-disable;
};
mux-mdio {
function = "mdio0";
groups = "mdio0_0_grp";
};
conf-mdio {
groups = "mdio0_0_grp";
slew-rate = <0>;
io-standard = <1>;
bias-disable;
};
};
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Test Procedure
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U-Boot 2018.01 Xilinx ZynqMP ZCU102 rev1.0
I2C: ready
DRAM: 4 GiB
EL Level: EL2
Chip ID: zuunknow
** Bad device mmc 0 **
Using default environment
In: serial@ff000000
Out: serial@ff000000
Err: serial@ff000000
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
Bootmode: JTAG_MODE
Net: ZYNQ GEM: ff0e0000, phyaddr c, interface rgmii-id
eth0: ethernet@ff0e0000
U-BOOT for xilinx-zcu102-2018_1
BOOTP broadcast 1
DHCP client bound to address 10.0.2.15 (3 ms)
Hit any key to stop autoboot: 0
ZynqMP> mii info
PHY 0x07: OUI = 0x5043, Model = 0x21, Rev = 0x00, 1000baseX, FDX
PHY 0x0C: OUI = 0x5043, Model = 0x21, Rev = 0x00, 1000baseX, FDX
ZynqMP>
ZynqMP> mii device
MII devices: 'eth0'
Current device: 'eth0'
ZynqMP>
ZynqMP> setenv <server_ip>
ZynqMP> ping <server_ip> |
HW IP features
- Speed support for 10/100/1000 Mbps
- MAC loopback and PHY loopback
- Partial store and forward option
- Packet buffer option
- Flow control - TX/RX pause
- Checksum offload support, CRC checking, FCS stripping
- Promiscuous mode, Broadcast mode
- Collision detection and enforcement - this is an IP feature, no SW support required
- MDIO support for PHY layer management
- Multicasting support
- VLAN tagged frames
- Half duplex support
- Programmable IPG
- External FIFO interface
- Wake on LAN
- IEEE1588 support for ZynqMP
- Jumbo frame size support for ZynqMP
- 64 bit addressing for ZynqMP
- Priority queue support for ZynqMP
- PS SGMII support (hardwired to 1Gbps) is present in ZynqMP
Features supported in driver
(Functional HW IP and stack related features)
- Speed support for 10/100/1000 Mbps with clock framework
- MDIO support for PHY layer management
- Multicasting support
- IEEE1588 support for ZynqMP
- Priority queue support for ZynqMP
- PS SGMII support is present in ZynqMP and supported in the driver
- This driver can be used with PL SGMII/1000BaseX driver on Zynq and ZynqMP
- This driver can be used with gmii2rgmii converter driver
- Fixed link support for ZynqMP(Not tested for Zynq).
Missing Features, Known Issues and Limitations
- 64-bit addressing support
Fixed Link Support in ZynqMP
Following are the steps to verify fixed link support in ZynqMP.
- Create a design with both GEM2 and GEM3 available and loop back one to the other as mention in below wiki
Zynq Ultrascale Fixed Link PS Ethernet Demo- Once the design is created export to sdk and create lwip echoserver application to run from R5 processor.
- In this application just confirm that it uses GEM2 in file src/platform_config.h
- In lwip echo server application linkerscript go and modify linker address to 0x10000000 such that it was not overwritten by FSBL or any other images.
- Go to bsp and change bsp settings to select uart1.
- Now got to the corresponding bsp and then to libsrc>lwip141>src>contrib>ports>xilinx>netif>xemacpsif_physpeed.c
- Open the file emacpsif_physpeed.c and go to routine phy_setup.c, comment the line "link_speed=get_IEEE_phy_speed(xemacpsp, phy_addr);" and assign link_speed=1000; Note that same speed should be given in u-boot dts.
- Now save and build it.
- Create FSBL for this design from SDK.
- Also create ATF and PMUFW.
- Now build u-boot for zcu102 with below changes in dts
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diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 5cbff57..db256e1 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -124,6 +124,11 @@
ti,fifo-depth = <0x1>;
ti,rxctrl-strap-worka;
};
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
};
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- Create a bootable BOOT.BIN using bif with images (pmufw, fsbl, bitstream, lwipapp, atf, u-boot).
- Copy the BOOT.BIN onto SD card and boot from SD on ZCU102 board.
- Open com0 port and you should see lwip prints and wait for print "TCP echo server started @ port 7".
- Now come back to u-boot prompt and set ipaddr as 192.168.1.1 using setenv.
- Now, ping lwip echoserver running on R5 from u-boot and it should success as shown below u-boot log.
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ZynqMP> setenv ipaddr 192.168.1.1
ZynqMP> ping 192.168.1.10
Using ethernet@ff0e0000 device
host 192.168.1.10 is alive
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