This page provides all the information related to Design Module 9 - VCU SDI Video Display design.
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1 Overview
The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks with the streaming use case where bandwidth plays a vital role.
This design supports the following video interfaces:
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For Petalinux related limitations please refer: PetaLinux 2020.1 - Product Update Release Notes and Known Issues
For VCU related limitations please refer AR# 66763: LogiCORE H.264/H.265 Video Codec Unit (VCU) - Release Notes and Known Issues, Xilinx Zynq UltraScale+ MPSoC Video Codec Unit and PG252 Link will be added <June-05> link.
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3 Appendix A - Input Configuration File (input.cfg)
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