...
The software architecture for this design is shown in Figure 5. The driver is divided into the following sections.
Initialization
MAC driver hooks
Interrupt service routines
References
AXI 1G/2.5G Ethernet Subsystem v7.0 Product Guide (PG138)
1G/2.5G Ethernet PCS/PMA or SGMII v16.0 LogiCORE IP Product Guide (PG047)
10G/25G High Speed Ethernet Subsystem v2.0 Product Guide (PG210)
PS and PL based Ethernet in Zynq MPSoC
Si570 Data Sheet (www.silabs.com/Support%20Documents/TechnicalDocs/Si570.pdf)
AXI DMA v7.1 LogiCORE IP Product Guide (PG021)
Netperf(www.netperf.org)
Xilinx Vivado Design Suite
PetaLinux
Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085)
ZCU102 Evaluation Board User Guide (UG1182)13.UltraScale Architecture GTH Transceivers User Guide (UG576)