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What is FSBL?


First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.
FSBL is loaded into OCM and handed off by CSU BootROM after authenticating and/or decrypting (as required) FSBL.

How to create FSBL from Vitis?

  • Launch VITIS with the below command: vitis
  • Provide path where VITIS workspace and project need to be created. With this VITIS workspace will be created
  • (Optional step) To work with local repos, Select "Xilinx" (ALT - x) -> Repositories. Against Local Repositories, click on "New..." and provide path of the local repo
  • Select File-->New-->Application Project to open "New Project" window, provide name for FSBL project
  • In the “Platform” section, click on “Create a new platform from hardware (XSA)” and select pre-defined hardware platform for ZynqMP (e.g. zcu102).
    • Alternatively, to create a new/custom platform from a .xsa file, click on “+”, browse and select the XSA file and a new hardware platform is created.
  • In the "Domain" window, select the processor psu_cortexa53_0/psu_cortexr5_0, OS as standalone and Language as C
  • Click Next and select "Zynq MP FSBL"
  • Click "Finish" to generate the A53/R5 FSBL. This populates the FSBL code and also builds it (along with BSP)
  • Debug prints in FSBL are now disabled by default (except for FSBL banner). To enable debug prints, define symbol: FSBL_DEBUG_INFO
    • In VITIS this can be done by: right click on FSBL application project -> select “C/C++ Build Settings” -> “Tool Settings” tab -> Symbols (under ARM v8 gcc compiler)
    • Click on Add (+) icon and Enter Value: FSBL_DEBUG_INFO, click on "OK" to close the "Enter Value" screen
  • In case any of the source files (FSBL or BSP) need to be modified, browse the file, make the change and save the file, build the project. elf file will be present in the Debug/Release folder of FSBL project.

What are various levels of debug prints in FSBL?

FSBL supports four levels of debug prints:
Type or printsPurposeEnabled by defining.. in FSBL codeAlternative way of enabling by defining symbol..
ALWAYSUsed for prints, which should be always enabled (e.g. FSBL banner)FSBL_PRINT_VAL to (1U)FSBL_PRINT
DEBUG GENERALTo print errors and basic general informationFSBL_DEBUG_VAL to (1U)FSBL_DEBUG
DEBUG INFOTo have more prints with format specifiers, in addition to basic general informationFSBL_DEBUG_INFO_VAL to (1U)FSBL_DEBUG_INFO
DEBUG DETAILEDTo have more detailed prints, in addition to above printsFSBL_DEBUG_DETAILED_VAL to (1U)FSBL_DEBUG_DETAILED

On what all processor cores can FSBL run on?

FSBL can only be run from A53_0 (AArch32 and AArch64), R5_0, R5_Lockstep

What part of OCM is used by FSBL?

OCM region used by FSBL: 0xFFFC0000 – 0xFFFE9FFF. The last 512 bytes of this region is used by FSBL to share the handoff parameters corresponding to applications ATF hands off. FSBL fully uses this OCM region and, in fact, in certain designs and when certain features need to enabled, the current footprint of FSBL doesn't fit in this available OCM. For details, search for "footprint" in this wiki.
ATF uses the rest of OCM i.e. from 0xFFFEA000 to 0xFFFFFFFF. Please note that the current implementation of APU-only restart assumes that FSBL "resides" in OCM even after its execution is complete. This is since, in such scenarios, PMUFW hands off to (already existing) FSBL without actually restarting.
Hence, OCM is completely used between FSBL and ATF and with the available APU-only restart mechanism, no other application can reuse it.

How is xfsbl_translation_table.S different from translation_table.S of BSP?

xfsbl_translation_table.S is a copy of file translation_table.S (of A53). The difference is that the FSBL’s copy of this file marks DDR region as reserved. This is to avoid speculative access to DDR before it is initialized. Once the DDR initialization is done in FSBL, memory attributes for DDR region is changed to “Memory” so that it is cacheable.

What ECC initialization is done by FSBL?

TCM ECC Initialization: When FSBL runs on R5, TCM ECC is always initialized. Also, when FSBL loads application targeted on R5, the corresponding TCM's ECC is initialized. When FSBL runs on A53, by default, TCM ECC is not initialized as this also involves powering up of RPU. In such cases, TCM ECC Initialization can be performed by defining FSBL_A53_TCM_ECC_EXCLUDE_VAL to 0 in xfsbl_config.h.
DDR ECC Initialization: Done in FSBL if ECC for DDR is enabled in design.

I’m unable to build FSBL due to size issues, how can I reduce its footprint?

FSBL provides option to enable/disable certain features from building. By selectively disabling certain features as mentioned in below table, code size can be reduced. These flags are defined in xfsbl_config.h of FSBL.
FLAGdefault valueMeaning of default setting / NotesSignificant impact on FSBL size?
FSBL_NAND_EXCLUDE_VAL(0U)NAND Boot mode related code is included (if NAND is present in design)Yes
FSBL_QSPI_EXCLUDE_VAL(0U)QSPI Boot mode related code is included (if QSPI is present in design)Yes
FSBL_SD_EXCLUDE_VAL(0U)SD Boot mode related code is included (if SD is present in design)Yes
FSBL_SECURE_EXCLUDE_VAL(0U)Secure features (Authenctication and decryption) are enabledYes
FSBL_BS_EXCLUDE_VAL(0U)PL Bitstream load capability is enabledYes
FSBL_SHA2_EXCLUDE_VAL(1U)SHA2 is not supportedYes
FSBL_EARLY_HANDOFF_EXCLUDE_VAL(1U)This flag/feature is not fully supported and hence is not recommended to change this settingNo
FSBL_WDT_EXCLUDE_VAL(0U)Watchdod timer feature is includedNo
FSBL_PERF_EXCLUDE_VAL(1U)Performance prints are not shown by defaultNo
FSBL_A53_TCM_ECC_EXCLUDE_VAL(1U)TCM ECC is not initialized for A53 ALWAYS. Changing this flag will result in TCM ECC being initialized always.No
FSBL_PL_CLEAR_EXCLUDE_VAL(1U)PL Initialization/clearing will be done ONLY when the boot image has PL bitstream. Changing this will result in PL Initialization/clearing to be done ALWAYS during FSBL InitializationNo
FSBL_USB_EXCLUDE_VAL(1U)USB Slave boot mode support is disabledYes
FSBL_PROT_BYPASS_EXCLUDE_VAL(1U)By default (from 2018.1), complete XMPU/XPPU configuration is done. Changing this flag will result in FSBL bypassing XPPU and FPD XMPU configuration and isolation/protection feature will be just limited to OCM slave.No
FSBL_PARTITION_LOAD_EXCLUDE_VAL(0U)By default FSBL loads all the partitions in the image, if this macro is been set, FSBL skips the partitions loading and will run the way it runs in JTAG boot mode.
FSBL_FORCE_ENC_EXCLUDE_VAL(0U)By default FSBL forces encryption of all the partitions when ENC_ONLY bit is blown, but if this macro is been set encryption can be optional for all the partitions loaded by FSBL, however it is compulsory for FSBL partition.

Are there any other ways by which FSBL footprint can be further reduced?

Debug prints: By default only FSBL banner is printed. If more debug prints are enabled, these will result in use of more memory.
Drivers Asserts: Asserts are used within all Xilinx drivers and can be turned off on a system-wide basis by defining, at compile time, the NDEBUG identifier (adding –DNDEBUG against extra_compiler_flags of drivers). This will help further reduce FSBL footprint.

I’m unable to debug FSBL in Vitis. Any change in optimizations used by FSBL?

For Starting in 2019.2, the FSBL will be built with –Os and LTO optimizations by default in VITIS.

In order to debug, the following are two options :

  •  Remove Optimizations
    1. Check "xfsbl_config.h" file, make sure that EXCLUDE flags options are not enabled/included. One thing to note here is that removing optimizations results in increase of code size and can result in not being able to build FSBL. In this case, the second option (of reducing optimization) can be looked at and followed.
  • Reduce/Change the level of Optimization - A two-step process. (Modify flags, BSP Settings) The first step can be done in three waysDisable Optimization flags -

    This prevents the view of C code in the debugger.

    To be able to view the C code during debug, these are few options:

    1.  Disable Optimization flags AND exclude unused FSBL code.
      1. In the "Miscellaneous" Section of FSBL app, remove highlighted options below.Image Modified                                                                                         In some cases, this would still   

    This would make the FSBL too big to

    not

    be able to fit in

    OCM and proceed with debug.Modify

    OCM and proceed with debug.  Make sure that EXCLUDE flags options are enabled in "xfsbl_config.h" if a feature is not used and can be excluded. If that doesn't free up enough space, the second option (of reducing optimization) can be looked at and followed.

    1. Reduce/Change the level of Optimization.
      1. Modify the flags to remove "-Os -flto -ffat-lto-objects" and include only "-O1 instead.                                                       Image Removed  " (optimization for code size and execution time) instead.
      2. If doing the above doesn't work and "-O1" is still difficult to debug, modify flags to remove "-Os -flto -ffat-lto-objects" and include "-Og" instead. "-Og" stands for Optimized Debug Experience. To be used along with this, some of the optimization flags can be tried manually.
        "-Og -finline-functions-called-once" is known to have worked.Refer to the following doc for

    REFERENCE: For more info on optimizationhttps://gcc.gnu.org/onlinedocs/gcc-8.2.0/gcc/Optimize-Options.html#Optimize-Options

    b. IMPORTANT NOTE: The following needs zynqmp_fsbl_bsp flag need to be done changed to FALSE after reducing opt by following removing or reducing the optimization (either of the three methods above).BSP settings: Highlighted zynqmp_fsbl_bsp flag need to be changed to false (to avoid turning on of optimization again of BSP for

    FSBL during rebuilding caused by above changeThis will avoid turning back-on of the FSBL BSP optimization during rebuilding.


    What are the memory regions and registers reserved for FSBL?

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