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The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
dmaps | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/dmaps | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/dmaps |
The driver source code is organized into different folders. The table below shows the dmaps driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl |
, .mdd file and .yaml files | |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmake files |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).
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Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples
Test Name | Example Source | Description |
|---|---|---|
DMAPS interrupt example | Basic DMAPS interrupt example demonstrating one transfer over first channel. |
Example Application Usage
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Basic DMAPS interrupt example demonstrating one transfer over first channel.
Expected Output
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Example Design Architecture
NA
Performance
NA
Change Log
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L554
2023.1
None
2022.2
None
2022.1
None
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L243
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