This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP Arasan SD 2.0 host controller.

Table of Contents

Table of Contents

Introduction

The SD/SDIO controller communicates with SDIO devices, SD memory cards, and MMC cards with up to four data lines. On the SD interface, one (DAT0) or four (DAT0-DAT3) lines can be used for data transfer. The SDIO interface can be routed through the MIO multiplexer to the MIO pins or through the EMIO to Select IO pin in the PL. The controller can support SD and SDIO applications in a wide range of portable low-power applications such as 802.11 devices, GPS, WiMAX, UWB, and others.
The SD/SDIO controller is compatible with the standard SD Host Controller Specification Version 2.0 Part A2 with SDMA (single operation DMA), ADMA1 (4 KB boundary limited DMA), and ADMA2 (ADMA2 allows data of any location and any size to be transferred in a 32-bit system memory-scatter-gather DMA) support. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. The Zynq-7000 SoC is expected to work with eMMC devices because the protocol is the same as SD, but this has not been extensively verified. Users must be careful to meet all timing requirements as they might or might not comply with eMMC. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards. The user should be familiar with the SD2.0/SDIO 2.0 specifications. The SD/SDIO controller also supports MMC3.31 standard. eMMC flash memories are not primary boot devices for Zynq-7000
family, but can be used as secondary boot devices.
The SD/SDIO controller is accessed by the Arm processor via the AHB bus. The controller also includes a DMA unit with an internal FIFO to meet throughput requirements.