...
Topic | Description | Development Board | Links | Latest Version |
---|---|---|---|---|
Multi-Rate GTY | This example describes a Versal GTY multi-rate design using the following configuration:
| VCK190/VMK180 | https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Multi-Rate%20GTY | 2020.2 |
Simplex TX/RX | This blog post shows how to combine Simplex TX/RX cores for several quads in IP Integrator | Any | 2020.2 | |
GTY Simulation | This blog entry covers a GTY simulation example, demonstrating how the GTY comes out of reset, and performs rate change. | Any | 2020.2 | |
Combine Within GT Quad | This example introduces the design flow on combining different IP within one quad with the Xilinx Vivado Integrated Design Environment. | VCK190 | https://github.com/Xilinx/XilinxCEDStore/tree/2020.2/ced/Xilinx/IPI/Versal%20Combine_within_GT_quad | 2020.2 |
GTY and GTY/GTYP | This blog post discusses the differences between designing with UltraScale+ GTY and Versal GTY/GTYP | N/A | N/A |
PCIe
Topic | Description | Development Board | Links | Latest Version |
---|---|---|---|---|
PCIe Link Debug Demo | This Blog entry is shows how to debug the Versal ACAP Integrated Block for PCIe Express link issues using in-built "PCIe Link Debug" feature. | VCK190 | 2020.2 |
...