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Code Block
pcap {
       compatible = "xlnx,zynqmp-pcap-fpga";
       clocks = <&clk 41>;

fpga_full: fpga-full {
       compatible = "fpga-region";
       fpga-mgr = <&pcap>;
       #address-cells = <2>;
       #size-cells = <2>;
	   power-domains = <&zynqmp_firmware PL_PD>;

For more details about  devicetree bindings Reference Below link: Devicetree


  • Above devicetree node is by default present in the zynqmp.dtsi file
  • power-domains:  Property is optional. If this property is present it controls the PM domain specifier as defined by bindings of the power controller specified by phandle.
    The PL_PD power domain will be turned on before loading the bitstream and turned off while removing/unloading the bitstream using overlays.

Bitstream Format

From 2018.3 release onwards FPGA Manager supports loading of vivado and bootgen generated Bitstream and Bin files vivadobootgen[1]