AXI MCDMA Standalone Driver
Table of Contents
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The Xilinx®
Table of Contents
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Introduction
The AXI MCDMA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides Scatter Gather interface with Multiple Channel support with independent configuration.
How to enable
Source Path for the driverFor more information, please refer to the AXI MCDMA product page which includes links to the official documentation and resource utilization.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
<If there are multiple drivers supporting this IP, we should make that statement here and add to the table>
| Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| mcdma | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mcdma_<version> | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/mcdma |
The driver source code is organized into different folders.
The table below shows the
axi mcdma driver source organization.
| Directory |
|---|
| Description |
|---|
| doc |
Provides the API and data structure details |
| data |
| Driver .tcl and |
| .mdd file |
| examples | Example applications that show how to use the driver |
|
- src-
| features | |
| src | Driver source files |
Features Supported
Controller Features
- AXI4 Compliant
- AXI4 data width support of 32, 64, 128, 256, 512 and 1,024 bits
- AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512 and 1,024 bits
- Supports up to 16 independent Channels
- Supports per Channel Interrupt output
- Supports DRE alignment for Streaming data Width of up to 512 bits
- Supports up to 64MB transfer per BD
- Optional AXIS Control and Status Streams
Driver Implementation
For a full list of features supported by this IP, please refer to the AXI MCDMA product page.
Features
The AXI MCDMA Standalone driver supports the following features: - Supports upto 16 Channels
- Supports Scatter/Gather Direct Memory Access (DMA)
- Supports 64-bit Addressing
- Supports Optional Data Re-Alignment Feature
- Supports per channel interrupt
- Supports AXIS Control and Status Streams.
Known Issues and Limitations
- All IP features are supported
Example Design Architecture
The examples assumes AXI MCDMA IP is configured in loopback mode.
Test cases
- Refer below pah for testing different examples for each feature of the IP.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mcdma/examples
| Test Name | Example Source | Description |
|---|---|---|
| Packet transfer with Interrupts | xmcdma_interrupt_example.c |
| This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode. | |
| Packet transfer with Polling | xmcdma_polled_example.c |
| This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode |
Known issues and Limitations
- All IP features are supported
Change Log
2020.2
- Support parallel make execution.
- Include XMcDma_BdGetAppWord() declaration in mcdma header.
4dc85994d6fb Makefile: Remove realpath command
21fc24b1bbaf mcdma: Update Makefile to support parallel make execution
e63225b263ef mcdma: Include XMcDma_BdGetAppWord() declaration in mcdma header
2020.1
- Prefer using dmb in XMcdma_UpdateChanTDesc
3232128 mcdma: Prefer using dmb in XMcdma_UpdateChanTDesc
2019.2
- None
2019.1
- Add HasRxLength field in config and channel structure
- Remove dependency on HPC_DESIGN macro
- In driver tcl enable CCI only for EL1 non-secure state
- Remove snooping enable from application
Commit ID:
e295490 mcdma: Add submit() variant to program additional BD fields
09087c8 mcdma: Add HasRxLength field in config and channel structure
7cf77a5 mcdma: Sync doxygen documentation
30f38de mcdma: examples: Remove dependency on HPC_DESIGN macro
9bcdf44 mcdma: In driver tcl enable CCI only for EL1 non-secure state
8937c2a mcdma: examples: Remove snooping enable from application
2018.3
- Support 64 bit DMA addresses for Microblaze-X
- Support hierarchical designs.
- Read buffer length register width and num channels from IP config.
- Code refactoring and fix gcc warning.
- Provide interface to do lookup by baseaddress and access Sw ID field in BD.
- Export APIs to use in LwIP202 contrib source.
Commit ID:
b87f96d Support 64 bit DMA addresses for Microblaze-X
04abde6 Update get_cells argument to support hierarchical designs
2984937 Read buffer length register width from IP config
f846cffe Fix typos and rephrase comment description
54d6909 Remove unused define for buffer length mask
b396c42 Enable 'Import Examples' link in system.mss
67b0f6d Fix gcc 'pointer from integer without a cast' warning
def3a92 Read num channels from IP configuration
d61b2f1 Add API to lookup config by base address
9542b71 Add macros to access Sw ID field in BD
debf203 Export APIs to use in LwIP202 contrib source
- None
- Fix bugs in the driver tcl
- Fix unused variable warning.
35c3c30 mcdma: Fix bugs in the driver tcl
bdc9deb mcdma: Fix unused variable warning
2017.4:
- None.
- Added support for MCDMA IP
6b7af95 : Initial version of the driver
Example Application Usage
Packet transfer with Interrupts
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in interrupt mode.
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
AXI MCDMA SG Interrupt Test passed
--- Exiting main() --- |
Packet transfer with Polling
This example demonstrates how to use axi mcdma driver on axi mcdma core to transfer packets in polled mode
Expected Output
| Code Block | ||
|---|---|---|
| ||
--- Entering main() ---
AXI MCDMA SG Polling Test passed
--- Exiting main() --- |
Change Log
2021.1
None
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L370
Related Links