| Table of Contents |
|---|
Introduction
This page gives an overview of UARTLite driver which is available as part of the Xilinx Vivado and SDK distribution.
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite core provides between
UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI interface and also provides
a controller interface for asynchronous serial data transfer. This soft LogiCORE™ IP core is designed to
interface with the AXI4-Lite protocol.
Source path for the driver:
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver name | Path in vitis | Path in github |
|---|---|---|
| uartlite | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartlite | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/ |
The driver source code is organized into different folders.
Below diagramThe table below shows the
iicpsuartlite driver source organization.
Directory |
|---|
Description |
|---|
doc |
Provides the API and data structure details |
|
- Examples - Reference application to
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver |
|
- Source - Driver source files
Controller Features Supported:
features | |
| src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf
Features
• AXI4-Lite interface for register access and data transfers• Full duplex
• 16-character transmit and receive FIFOs
• Configurable number of data bits (5-8) in a character
• Configurable parity bit (odd or even or none)
• Configurable baud rate
Driver Supported Features
The UARTLite Standalone driver support the below things.All Controller Features supported.
Known issues
Known Issues and Limitations
None
.Test casesExample Applications
Refer
...
to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite/examples
ChangeLog
2017.1Summary:
- uartlite: Added xil_printf statement in examples.
- uartlite: Updated makefile.
- uartlite: Added readme.txt file to generate doxygen for examples
- 161c1b8 uartlite: Added xil_printf statement in examples.
- 4ba7f29 uartlite: Updated makefile.
- c3c4385 uartlite: Added readme.txt file to generate doxygen for examples
- None
- None
- None
2018.1
- None
2018.2
- None
2018.3
- None
2019.1
- None
2019.2
- None
2020.1
- Summary
- drivers: Fix makefiles issue for windows
- Commits
- Summary
2020.2
None| Test Name | Example Source | Description |
|---|---|---|
| Uartlite interrupt example | xuartlite_intr_example.c | This example sends and receives data using interrupts. |
| Uartlite polled example | xuartlite_polled_example.c | This example sends and receives data using polling. |
| Uartlite tapp interrupt example | xuartlite_intr_tapp_example.c | This example just transmits the data using interrupts. |
Example Application Usage
Uartlite interrupt example
This example sends and receives data using interrupts.| Code Block |
|---|
Successfully ran Uartlite interrupt Example |
Uartlite polled example
This example sends and receives data using polling.
Expected Output
| Code Block |
|---|
Successfully ran Uartlite polled Example |
Uartlite tapp interrupt example
This example just transmits the data using interrupts.| Code Block |
|---|
Successfully ran Uartlite interrupt tapp Example |
Example Design Architecture
NA
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L483
2020.2
None
2020.1
None
2019.2
None
2019.1
None
2018.3
None