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| Table of Contents |
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Introduction
This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.
For more information, please refer TRM which includes links to the official documentation and resource utilization.
Source path for the driver:
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| clk_wiz | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/clk_wiz | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz |
| Info |
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Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz |
Driver The driver source code is organized into different folders. Below diagram The table below shows the clk_wiz driver source organization. ospipsv
| Directory | Description |
|---|
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doc |
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Provides the API and data structure details |
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data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver |
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features | |
| src | Driver source files |
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Driver Implementation
For a full list of features supported by this IP, please refer TRM
Features
- Accepts up to two input clocks and up to
seven output clocks per clock network. - Provides an AXI4-Lite interface for
dynamically reconfiguring the clocking
primitives for Multiply, Divide, Phase Shift/
Offset, or Duty Cycle.
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Known Issues and Limitations
- None
Test cases
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Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz/examples
| Test Name | Example Source | Description |
|---|---|---|
| Clocking wizard versal example |
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| Example to set the output frequency to a specific rate for versal platform. |
Change Log
2020.1
2020.2
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| Clocking wizard Interrupt mode example | This example tests the clock monitoring example |
Example Application Usage
Clock Wizard versal example
This examples does basic rate setting of clocking wizard.
Expected Output
| Code Block |
|---|
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CLK_WIZARD example
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Successfully ran CLK_WIZARD example
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Clock Wizard Interrupt mode example
This example tests the clock monitoring example
Expected Output
| Code Block |
|---|
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CLK_WIZARD example
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Successfully ran CLK_WIZ Monitor interrupt example
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Example Design Architecture
NA
Performance
NA
Change Log
2021.1
None
2020.2
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L1170
2020.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2100