Axi traffic generator
Introduction
This page gives an overview of axi traffic generator driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® LogiCORE™ IP AXI traffic generator core is a soft Xilinx IP core for
Use with the Xilinx Vivado® Design Suite.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
---|---|---|
trafgen | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/trafgen | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen |
Info |
---|
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/ospipsv |
The driver source code is organized into different folders. The table below shows the ospipsv driver source organization.
Directory | Description |
---|---|
doc | Provides the API and data structure details |
data | Driver .tcl and .mdd file |
examples | Example applications that show how to use the driver features |
src | Driver source files |
Driver Implementation
For a full list of features supported by this IP, please refer TRM
Features
- Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
128/256/512-bit) on output AXI4-memory map Master interface - Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
- AXI4-stream Master/Slave interface
- Interrupt support for indicating completion for traffic generation.
- Error interrupt pin indicating error occurred during core operation. Error registers can
be read to understand the error occurred.
Known Issues and Limitations
- None
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen/examples
Test Name | Example Source | Description |
---|---|---|
Trafgen Polled mode example | This example programs known data to master RAM and command to command ram and param ram. The data will be taken from master RAM and programmed to the slave. | |
Trafgen Interrupt mode example | This example programs known data to master RAM and command to command ram and param ram. The data will be taken from master RAM and programmed to the slave in interrupt mode. | |
Trafgen Streaming example | xtrafgen_master_streaming_example.c | This examples does basic read and write test from the flash device in Non-blocking Polled mode. |
Example Application Usage
Trafgen Polled mode example
This example programs known data to master RAM and command to command ram and param ram. The data will
be taken from master RAM and programmed to the slave.
Expected Output
OSPI Interrupt mode exampleCode Block |
---|
Entering main |
--- Exiting main() --- |
Successfully ran Traffic Generator |
This examples does basic read and write test from the flash device in Interrupt mode.
Expected Output
Code Block |
---|
OSPIPSV Flash Interrupt Polling Example Test Execuing on the a72 FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0 EraseCmd 0xDC WriteCmd: 0x12 ReadCmd 0xCC Successfully ran OSPIPSV Flash Interrupt Example |
OSPI Non-blocking Polled mode example
This examples does basic read and write test from the flash device in Non-blocking Polled mode.
Expected Output
Code Block |
---|
OSPIPSV Flash Polled non-blocking read Example Test FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0 EraseCmd 0xDC WriteCmd: 0x12 ReadCmd 0xCC Successfully ran OSPIPSV Flash non-blocking read Ex |
Trafgen I Interrupt mode example
Expected Output
Code Block |
---|
Successfully ran Traffic Generator Interrupt Example |
Example Design Architecture
NA
Performance
NA
Change Log
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L459
AXI Traffic generator Standalone Driver
IntroductionSource Path for the driver
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen
Driver source code is organized into different folders. Below diagram shows the trafgen driver source organization
ATG
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
HW IP features
- Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
128/256/512-bit) on output AXI4-memory map Master interface - Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
- AXI4-stream Master/Slave interface
- Interrupt support for indicating completion for traffic generation.
- Error interrupt pin indicating error occurred during core operation. Error registers can
be read to understand the error occurred.
Features supported in driver
The AXI Traffic generator Standalone driver support the below things.Missing Features, Known Issues and Limitations
NoneTest Procedure
Refer below path for testing different examples for each feature of the IP.https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/trafgen/examples
xtrafgen_interrupt_example.c :
xtrafgen_polling_example.c :
xtrafgen_static_mode_example.c : This example demonstrates how to use axi traffic generator in static mode.
xtrafgen_master_streaming_example.c : This example demonstrates how to use axi traffic generator in streaming mode.
Change Log
2017.1- None
- None
- None
2017.4
- None
2018.1
- None
2018.2
- None
2018.3
- None
2019.1
- Summary:
- Changes in Makefile to make map file consistent in windows & other platforms.
- Commits:
- 2700c6b: Changes in Makefile to make map file consistent in windows & other platforms.
2019.2
- None
2020.1
- None
2020.2
- trafgen: Update Makefile for parallel make execution
- Makefile: Remove realpath command
2020.2
None
2020.1
None
2019.2
None