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  1. Copy the QNX Initial Program Loader (IPL) (<qnx proj dir>/prebuilt/aarch64le/boot/sys/ipl-xzynq-ultrascale-zcu10x) to the folder that includes the provided 2019.1 VCU TRD bootfiles. Rename the file to ipl-xzynq-ultrascale-zcu10x.elf.

  2. Open an xsct command shell, cd to the boot files directory, and use the Xilinx Bootgen tool to generate BOOT.BIN with the following command:

    Code Block
    bootgen -image boot_vcu_trd.bif -arch zynqmp -o BOOT.BIN -w

Here is an example boot_vcu_trd.bif:

Code Block
	[bootloader,destination_cpu=a53-0] vcu_trd/zynqmp_fsbl.elf
	[destination_cpu=pmu] pmufw.elf
	[destination_device = pl] vcu_trd/vcu_trd_wrapper.bit
	[destination_cpu=a53-0,exception_level=el-3,trustzone] bl31.elf
	[destination_cpu=a53-0,exception_level=el-2] ipl-xzynq-zcu102.elf

Preparing the Hardware

By default, this reference design targets the 2019.1 VCU TRD Design Module #1. With modification, other similar hardware configurations can be supported as well - please refer to Appendix A below. From a QNX software perspective, this reference design supports a subset of the VCU TRD interfaces as defined below: