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The documents every Versal NoC and DDR MC user needs are:
UG1304 - Versal ACAP Adaptive SoC System Software Developers Guide
Answer Record 75764: Versal ACAP Adaptive SoC Programmable Network on Chip and Integrated Memory Controller - IP Release Notes and Known Issues
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Tutorial: Obtaining and Verifying Versal ACAP Adaptive SoC Memory Pinouts
Tutorial: DDR4 and LPDDR4 Timing Models for Hyperlinx DDRx Wizard in Versal ACAPsAdaptive SoCs
Pinout Rules in PG313
Answer Record 76059: Versal ACAP Adaptive SoC DDRMC - DDR4 and LPDDR4/x PCB Simulation Support
Appendix A: Memory Interface Debug in PG313
Chapter 7: Boot and Configuration and Chapter 8: Platform Loader and Manager in UG1304
This document lists PLM error codes
Blog: A Brief Overview of the Versal Boot Files summarizes these chapters
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This user needs to know how to use Vivado to create an ACAP Adaptive SoC design. The modules in the Introduction to NoC DDRMC Design Flow walk through the basics of how to create a NoC and DDR MC design in IPI while the other resources show how to integrate with other IPs.
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Tutorial: Modules 1-5 of Introduction to NoC DDRMC Design Flow
Blog: Basic read/write to AXI BRAM from PS-APU through NoC in Versal
CEDStore: AXI DMA on VCK190
Tutorial: Versal Embedded Design, section on Versal ACAP Adaptive SoC CIPS and NoC (DDR) IP Core Configuration
CEDStore: VCK190/VMK190 Configurable Example Design in Vivado
CEDStore: Simulating with the CIPS Verification IP
Example: Versal Network on Chip/Multiple DDR Memory Controllers Tutorial
System Integration and Validation
This user brings together the ACAP Adaptive SoC hardware, board design and software and needs system level debug tools to diagnose and resolve performance and power issues.
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