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Zynq UltraScale+ MPSoC VCU TRD 2019.1 - HDMI Video Display

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Table of Contents

Table of Contents
excludeZynq UltraScale+ MPSoC VCU TRD 2018.3 - HDMI Video Display

1 Overview

The primary goal of this Design is to demonstrate the capabilities of VCU hard block present in Zynq UltraScale+ EV devices. The TRD will serve as a platform to tune the performance parameters of VCU and arrive at optimal configurations for encoder and decoder blocks with the streaming use case where bandwidth plays a vital role. 

This design supports the following video interfaces:


  • File source (SD card, USB storage, SATA hard disk).
  • Stream-In from network or internet.


  • HDMI-Tx display pipeline implemented in the PL.

VCU Codec:

  • Video Encode/Decode capability using VCU hard block in PL 
    • AVC/HEVC encoding.
    • Encoder/decoder parameter configuration.

Streaming Interfaces:

  • 1G Ethernet on PS 

Video format:

  • NV12

10G Deliverables:


Input source

Output Type


Video encode/Decoder type


Playback pipeline

File Source/ Stream-In




Playback of the local-file/stream-in with video decoded using VCU and display on  HDMI-Tx.

Supported Features:

The table below provides the supported encoder feature in this release.

Command Line
Single StreamMulti-stream

√ - Supported
NA – Not applicable
x – Not supported

The below figure shows the HDMI Video Display design hardware block diagram.

The below figure shows the HDMI Video Display design software block diagram.

1.1 Board Setup

Refer below link for Board Setup