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This page gives and overview of the bare metal driver for the Xi= linx=C2=AE LogiCORE=E2=84=A2 IP Zynq=C2=AE UltraScale+=E2=84=A2 RFSoC RF Da= ta Converter
The Xilinx=C2=AE LogiCORE=E2=84=A2 IP Zynq=C2=AE UltraScale+=E2=84=A2 RF= SoC RF Data Converter IP core provides a configurable wrapper to allow the = RF-DAC and RF-ADC blocks to be used in IP integrator designs.
For more information, please refer to https://www.xilinx.com/products/boards-and-kits/zcu208.html , https://www.xilinx.com/products/boards-and= -kits/zcu216.html & https://w= ww.xilinx.com/products/boards-and-kits/zcu111.html .
The source code for the driver is included with the Vitis Unified Softwa= re Platform installation, as well as being available in the Xilinx Github r= epository.
Driver Name |
Path in Vitis |
Path in Github |
---|---|---|
rfdc |
<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drive= rs/rfdc_v10_0 |
https://git= hub.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/rfdc= |
Note: To view the sources for a particular release, use the rel-version = tag in github. For example, for the 2020.1 release, the proper versio= n of the code is:
htt= ps://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/= drivers/rfdc
The driver source code is organized into different folders. The ta= ble below shows the <Driver Name> driver source organization. = p>
Directory |
Description |
---|---|
doc |
Provides the API and data structure details |
data |
Driver .tcl and .mdd file |
examples |
Example applications that show how to use the driver features |
src |
Driver source files |
Refer to the driver examples directory for various example applications = that exercise the different features of the driver. Each application is lin= ked in the table below. The following sections describe the usage and expec= ted output of the various applications. These example applications ca= n be imported into the Vitis IDE from the Board Support Package setti= ngs tab.
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/driv=
ers/rfdc/examples
Test Name |
Example Source |
Description |
---|---|---|
Self Test |
This example does some writes to the hardware to do some sanity checks.<= /p> |
|
Read/Write Test |
This example uses multiple driver "set" APIs to configure the targeted* = AMS block.* Subsequently it uses "get" APIs to read back the configurations= to ensure that the desired configurations are applied. |
|
Multi Tile Sync Example |
This example demonstrates the multi-tile sync functionality |
|
Interrupt Example |
This example shows the interrupts working |
|
Clocked Gen 3 Example |
This example shows how to set the clocks for Gen 3 devices |
|
Clocked Gen 2 Example |
This example shows how to set the clocks for Gen 3 devices |
This example does some writes to the hardware to do some sanity checks.<= /p>
Expected Output
RFdc Sel= ftest Example Test Successfully ran Selftest Example Test
This example does some writes to the hardware to do some sanity checks.<= /p>
Expected Output
RFdc Rea= d and Write Example Test DAC00 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC00 Output Current is 32025mA ADC00 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 ADC00: Link Coupling Mode is 1 DAC01 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC01 Output Current is 32025mA ADC01 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 ADC01: Link Coupling Mode is 1 DAC02 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC02 Output Current is 32025mA DAC03 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC03 Output Current is 32025mA ADC0 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 Out= putDivider is 6 ReferenceClk Divider is 1 DAC0 PLL Configurations:: PLL Enable is 1 Feedback Divider is 32 Out= putDivider is 2 ReferenceClk Divider is 1 DAC10 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC10 Output Current is 32025mA ADC10 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 ADC10: Link Coupling Mode is 1 DAC11 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC11 Output Current is 32025mA DAC12 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC12 Output Current is 32025mA DAC13 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 DAC13 Output Current is 32025mA ADC1 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 Out= putDivider is 6 ReferenceClk Divider is 1 DAC1 PLL Configurations:: PLL Enable is 1 Feedback Divider is 32 Out= putDivider is 2 ReferenceClk Divider is 1 ADC20 Status DataPathClockStatus - 1 IsFIFOFlagsEnabled - 3 IsFIFOFlag= sAsserted - 0 ADC20: Link Coupling Mode is 1 ADC2 PLL Configurations:: PLL Enable is 1 Feedback Divider is 48 Out= putDivider is 3 ReferenceClk Divider is 1 =3D=3D=3D=3D=3D=3D=3DDefault DigitalDataPath Configuration for Tile0=3D=3D= =3D=3D=3D=3D DAC DigitalDataPath0-> Connected I data =3D 0 DAC DigitalDataPath0-> Connected Q data =3D -1 ADC DigitalDataPath0-> Connected I data =3D 0 ADC DigitalDataPath0-> Connected Q data =3D -1 DAC DigitalDataPath1-> Connected I data =3D 1 DAC DigitalDataPath1-> Connected Q data =3D -1 ADC DigitalDataPath1-> Connected I data =3D 1 ADC DigitalDataPath1-> Connected Q data =3D -1 DAC DigitalDataPath2-> Connected I data =3D 2 DAC DigitalDataPath2-> Connected Q data =3D -1 ADC DigitalDataPath2-> Connected I data =3D 2 ADC DigitalDataPath2-> Connected Q data =3D -1 DAC DigitalDataPath3-> Connected I data =3D 3 DAC DigitalDataPath3-> Connected Q data =3D -1 ADC DigitalDataPath3-> Connected I data =3D 3 ADC DigitalDataPath3-> Connected Q data =3D -1 ADC0 MB Config is 0 DAC0 MB Config is 0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DADC0-4G SB Configuration R2C=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D ADC DigitalDataPath0-> Connected I data =3D 0 ADC DigitalDataPath0-> Connected Q data =3D -1 ADC DigitalDataPath1-> Connected I data =3D 1 ADC DigitalDataPath1-> Connected Q data =3D -1 ADC DigitalDataPath2-> Connected I data =3D 2 ADC DigitalDataPath2-> Connected Q data =3D -1 ADC DigitalDataPath3-> Connected I data =3D 3 ADC DigitalDataPath3-> Connected Q data =3D -1 ADC0 MB Config is 0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DADC0,1-4G MB Configuration R2C=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D ADC DigitalDataPath0-> Connected I data =3D 0 ADC DigitalDataPath0-> Connected Q data =3D -1 ADC DigitalDataPath1-> Connected I data =3D 0 ADC DigitalDataPath1-> Connected Q data =3D -1 ADC DigitalDataPath2-> Connected I data =3D 2 ADC DigitalDataPath2-> Connected Q data =3D -1 ADC DigitalDataPath3-> Connected I data =3D 3 ADC DigitalDataPath3-> Connected Q data =3D -1 ADC0 MB Config is 1 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DADC0,1-4G MB Configuration C2C=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D ADC DigitalDataPath0-> Connected I data =3D 0 ADC DigitalDataPath0-> Connected Q data =3D 1 ADC DigitalDataPath1-> Connected I data =3D 0 ADC DigitalDataPath1-> Connected Q data =3D 1 ADC DigitalDataPath2-> Connected I data =3D 2 ADC DigitalDataPath2-> Connected Q data =3D -1 ADC DigitalDataPath3-> Connected I data =3D 3 ADC DigitalDataPath3-> Connected Q data =3D -1 ADC0 MB Config is 1 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DADC0,1-4G SB Configuration R2C=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D ADC DigitalDataPath0-> Connected I data =3D 0 ADC DigitalDataPath0-> Connected Q data =3D -1 ADC DigitalDataPath1-> Connected I data =3D 1 ADC DigitalDataPath1-> Connected Q data =3D -1 ADC DigitalDataPath2-> Connected I data =3D 2 ADC DigitalDataPath2-> Connected Q data =3D -1 ADC DigitalDataPath3-> Connected I data =3D 3 ADC DigitalDataPath3-> Connected Q data =3D -1 ADC0 MB Config is 0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3DDAC0 SB Configuration C2R=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D DAC DigitalDataPath0-> Connected I data =3D 0 DAC DigitalDataPath0-> Connected Q data =3D -1 DAC DigitalDataPath1-> Connected I data =3D 1 DAC DigitalDataPath1-> Connected Q data =3D -1 DAC DigitalDataPath2-> Connected I data =3D 2 DAC DigitalDataPath2-> Connected Q data =3D -1 DAC DigitalDataPath3-> Connected I data =3D 3 DAC DigitalDataPath3-> Connected Q data =3D -1 DAC0 MB Config is 0 =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D DAC2,3 MB Config is 2 DAC 4X MB Config is 4 DAC0,1 MB Config is 3 DAC2,3 MB Config is 3 DAC0, 1 SB Config is 2 DAC2, 3 SB Config is 0 Successfully ran Read and Write Example
This example does some writes to the hardware to do some sanity checks.<= /p>
Expected Output
RFdc Fab= ric Interrupt Example Test registered stim block. registered cap block. registered IPI interrupt. Waiting for Interrupt Successfully ran RFdc Fabric Interrupt Example Test
http=
s://github.com/Xilinx/embeddedsw/commits/master/XilinxProcessorIPLib/driver=
s/rfdc
This page gives an overview of the bare-metal driver support for th= e Xilinx=C2=AE Zynq UltraScale+ RFSoC RF Data Converter.