Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedThu Aug 13 16:21:20 2015 product_versionVivado v2015.1 (64-bit)
build_version1205919 os_platformWIN64
registration_id1_2_4_3 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a35ti
target_packagecsg324 target_speed-1L
random_id4bcafb664c2a59f596b17337fade1dc8 project_idd2346d413b994bc2b3a3d5ba4ba0ec9c
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-2720QM CPU @ 2.20GHz cpu_speed2195 MHz
total_processors1 system_ram4.000 GB

vivado_usage
project_data
srcsetcount=4 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1 board=Arty1

unisim_transformation
pre_unisim_transformation
and2b1l=2 bscane2=1 bufg=10 bufh=2
carry4=446 dsp48e1=6 fdce=387 fdpe=103
fdre=14610 fdse=352 gnd=846 ibuf=17
idelayctrl=1 idelaye2=16 in_fifo=2 iobuf=1
iobufds_intermdisable=2 iobuf_intermdisable=16 iserdese2=16 lut1=581
lut2=1724 lut3=2849 lut4=2218 lut5=2523
lut6=4199 lut6_2=64 mmcme2_adv=2 muxf7=196
muxf8=2 obuf=45 obufds=1 obuft=2
oddr=5 oserdese2=43 out_fifo=4 phaser_in_phy=2
phaser_out_phy=4 phaser_ref=1 phy_control=1 plle2_adv=1
ram32m=159 ram32x1d=32 ram32x1s=4 ramb36e1=31
srl16e=231 srlc16e=7 srlc32e=265 vcc=490
xadc=1
post_unisim_transformation
and2b1l=2 bscane2=1 bufg=10 bufh=2
carry4=446 dsp48e1=6 fdce=387 fdpe=103
fdre=14610 fdse=352 gnd=846 ibuf=18
ibufds_intermdisable_int=4 ibuf_intermdisable=16 idelayctrl=1 idelaye2=16
inv=3 in_fifo=2 iserdese2=16 lut1=581
lut2=1724 lut3=2849 lut4=2218 lut5=2587
lut6=4263 mmcme2_adv=2 muxf7=196 muxf8=2
obuf=45 obufds=2 obuft=19 obuftds=4
oddr=5 oserdese2=43 out_fifo=4 phaser_in_phy=2
phaser_out_phy=4 phaser_ref=1 phy_control=1 plle2_adv=1
ramb36e1=31 ramd32=1018 rams32=322 srl16e=231
srlc16e=7 srlc32e=265 vcc=490 xadc=1

placer
usage
lut=12396 ff=10767 bram36=31 bram18=0
ctrls=510 dsp=6 iob=87 bufg=0
global_clocks=9 pll=1 bufr=0 nets=34130
movable_instances=28491 pins=170073 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=90.059000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=10765 srls_augmented=0
srls_newly_gated=0 srls_total=501 bram_ports_augmented=0 bram_ports_newly_gated=4
bram_ports_total=62 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=BlockDiagram
x_ipname=design_1 x_ipversion=1.00.a x_iplanguage=VERILOG numblks=36
numreposblks=22 numnonxlnxblks=0 numhierblks=14 maxhierdepth=1
da_axi4_cnt=8 da_board_cnt=12 da_mb_cnt=1 synth_mode=Global
MDM/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=mdm x_ipversion=3.2 x_ipcorerevision=2 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_jtag_chain=2 c_use_bscan=0
c_use_config_reset=0 c_interconnect=2 c_mb_dbg_ports=1 c_use_uart=0
c_dbg_reg_access=0 c_dbg_mem_access=0 c_use_cross_trigger=0 c_trace_output=0
c_trace_data_width=32 c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_s_axi_addr_width=32
c_s_axi_data_width=32 c_s_axi_aclk_freq_hz=100000000 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_thread_id_width=1 c_data_size=32 c_m_axis_data_width=32 c_m_axis_id_width=7
MicroBlaze/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=microblaze x_ipversion=9.5 x_ipcorerevision=0 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_sco=0 c_freq=83250000 c_use_config_reset=0
c_num_sync_ff_clk=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_clk_debug=2 c_num_sync_ff_dbg_clk=1
c_fault_tolerant=0 c_ecc_use_ce_exception=0 c_lockstep_slave=0 c_endianness=1
c_family=artix7 c_data_size=32 c_instance=design_1_microblaze_0_0 c_avoid_primitives=0
c_area_optimized=0 c_optimization=0 c_interconnect=2 c_base_vectors=0x00000000
c_m_axi_dp_thread_id_width=1 c_m_axi_dp_data_width=32 c_m_axi_dp_addr_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_d_bus_exception=0 c_m_axi_ip_thread_id_width=1 c_m_axi_ip_data_width=32 c_m_axi_ip_addr_width=32
c_m_axi_i_bus_exception=0 c_d_lmb=1 c_d_axi=1 c_i_lmb=1
c_i_axi=0 c_use_msr_instr=1 c_use_pcmp_instr=1 c_use_barrel=1
c_use_div=1 c_use_hw_mul=2 c_use_fpu=2 c_use_reorder_instr=1
c_unaligned_exceptions=0 c_ill_opcode_exception=0 c_div_zero_exception=0 c_fpu_exception=0
c_fsl_links=0 c_use_extended_fsl_instr=0 c_fsl_exception=0 c_use_stack_protection=0
c_imprecise_exceptions=0 c_use_interrupt=2 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_mmu=0 c_mmu_dtlb_size=4 c_mmu_itlb_size=2 c_mmu_tlb_access=3
c_mmu_zones=2 c_mmu_privileged_instr=0 c_use_branch_target_cache=1 c_branch_target_cache_size=0
c_pc_width=32 c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000
c_dynamic_bus_sizing=0 c_reset_msr=0x00000000 c_opcode_0x0_illegal=0 c_debug_enabled=1
c_number_of_pc_brk=1 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_debug_event_counters=5
c_debug_latency_counters=1 c_debug_counter_width=32 c_debug_trace_size=8192 c_debug_external_trace=0
c_debug_profile_size=0 c_interrupt_is_edge=0 c_edge_is_positive=1 c_async_interrupt=1
c_m0_axis_data_width=32 c_s0_axis_data_width=32 c_m1_axis_data_width=32 c_s1_axis_data_width=32
c_m2_axis_data_width=32 c_s2_axis_data_width=32 c_m3_axis_data_width=32 c_s3_axis_data_width=32
c_m4_axis_data_width=32 c_s4_axis_data_width=32 c_m5_axis_data_width=32 c_s5_axis_data_width=32
c_m6_axis_data_width=32 c_s6_axis_data_width=32 c_m7_axis_data_width=32 c_s7_axis_data_width=32
c_m8_axis_data_width=32 c_s8_axis_data_width=32 c_m9_axis_data_width=32 c_s9_axis_data_width=32
c_m10_axis_data_width=32 c_s10_axis_data_width=32 c_m11_axis_data_width=32 c_s11_axis_data_width=32
c_m12_axis_data_width=32 c_s12_axis_data_width=32 c_m13_axis_data_width=32 c_s13_axis_data_width=32
c_m14_axis_data_width=32 c_s14_axis_data_width=32 c_m15_axis_data_width=32 c_s15_axis_data_width=32
c_icache_baseaddr=0x80000000 c_icache_highaddr=0x8fffffff c_use_icache=1 c_allow_icache_wr=1
c_addr_tag_bits=14 c_cache_byte_size=16384 c_icache_line_len=8 c_icache_always_used=1
c_icache_streams=1 c_icache_victims=4 c_icache_force_tag_lutram=0 c_icache_data_width=0
c_m_axi_ic_thread_id_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_addr_width=32 c_m_axi_ic_user_value=31
c_m_axi_ic_awuser_width=5 c_m_axi_ic_aruser_width=5 c_m_axi_ic_wuser_width=1 c_m_axi_ic_ruser_width=1
c_m_axi_ic_buser_width=1 c_dcache_baseaddr=0x80000000 c_dcache_highaddr=0x8fffffff c_use_dcache=1
c_allow_dcache_wr=1 c_dcache_addr_tag=14 c_dcache_byte_size=16384 c_dcache_line_len=8
c_dcache_always_used=1 c_dcache_use_writeback=1 c_dcache_victims=4 c_dcache_force_tag_lutram=0
c_dcache_data_width=0 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_data_width=32 c_m_axi_dc_addr_width=32
c_m_axi_dc_exclusive_access=0 c_m_axi_dc_user_value=31 c_m_axi_dc_awuser_width=5 c_m_axi_dc_aruser_width=5
c_m_axi_dc_wuser_width=1 c_m_axi_dc_ruser_width=1 c_m_axi_dc_buser_width=1
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=2 c_num_master_slots=1
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=128 c_axi_protocol=0
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000080000000 c_m_axi_addr_width=0x0000001c c_s_axi_base_id=0x0000000100000000
c_s_axi_thread_id_width=0x0000000000000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001
c_m_axi_read_connectivity=0x00000003 c_r_register=0 c_s_axi_single_thread=0x0000000000000000 c_s_axi_write_acceptance=0x0000000200000008
c_s_axi_read_acceptance=0x0000000800000002 c_m_axi_write_issuing=0x00000008 c_m_axi_read_issuing=0x00000008 c_s_axi_arb_priority=0x0000000000000000
c_m_axi_secure=0x00000000 c_connectivity_mode=1
axi_crossbar_v2_1_axi_crossbar/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=7
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000040010000000000004000000000000000406000000000000041c100000000000041c000000000000040e000000000000041200000 c_m_axi_addr_width=0x00000010000000100000001000000010000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000001000000010000000100000001000000010000000100000001
c_m_axi_read_connectivity=0x00000001000000010000000100000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x00000001000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x00000001000000010000000100000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x00000000000000000000000000000000000000000000000000000000 c_connectivity_mode=0
axi_dwidth_converter_v2_1_top/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_dwidth_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_axi_protocol=0 c_s_axi_id_width=1
c_supports_id=0 c_axi_addr_width=32 c_s_axi_data_width=32 c_m_axi_data_width=128
c_axi_supports_write=1 c_axi_supports_read=1 c_fifo_mode=0 c_s_axi_aclk_ratio=1
c_m_axi_aclk_ratio=2 c_axi_is_aclk_async=0 c_max_split_beats=16 c_packing_level=1
c_synchronizer_stage=3
axi_dwidth_converter_v2_1_top/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_dwidth_converter x_ipversion=2.1 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_axi_protocol=0 c_s_axi_id_width=1
c_supports_id=0 c_axi_addr_width=32 c_s_axi_data_width=32 c_m_axi_data_width=128
c_axi_supports_write=0 c_axi_supports_read=1 c_fifo_mode=0 c_s_axi_aclk_ratio=1
c_m_axi_aclk_ratio=2 c_axi_is_aclk_async=0 c_max_split_beats=16 c_packing_level=1
c_synchronizer_stage=3
axi_ethernetlite/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_ethernetlite x_ipversion=3.0 x_ipcorerevision=3 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_instance=axi_ethernetlite_inst c_s_axi_aclk_period_ps=12012
c_s_axi_addr_width=13 c_s_axi_data_width=32 c_s_axi_id_width=1 c_s_axi_protocol=AXI4LITE
c_include_mdio=1 c_include_internal_loopback=0 c_include_global_buffers=1 c_duplex=1
c_tx_ping_pong=1 c_rx_ping_pong=1
axi_gpio/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=12 c_gpio2_width=32 c_all_inputs=0 c_all_inputs_2=0
c_all_outputs=1 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=4 c_gpio2_width=32 c_all_inputs=1 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_intc/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_intc x_ipversion=4.1 x_ipcorerevision=3 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_instance=axi_intc_inst c_s_axi_addr_width=9
c_s_axi_data_width=32 c_num_intr_inputs=4 c_num_sw_intr=0 c_kind_of_intr=0xfffffff5
c_kind_of_edge=0xffffffff c_kind_of_lvl=0xffffffff c_async_intr=0xFFFFFFF0 c_num_sync_ff=2
c_ivar_reset_value=0x00000010 c_enable_async=0 c_has_ipr=1 c_has_sie=1
c_has_cie=1 c_has_ivr=1 c_has_ilr=0 c_irq_is_level=1
c_irq_active=0x1 c_disable_synchronizers=1 c_mb_clk_not_connected=1 c_has_fast=1
c_en_cascade_mode=0 c_cascade_master=0
axi_timer/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_timer x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_count_width=32 c_one_timer_only=0
c_trig0_assert=1 c_trig1_assert=1 c_gen0_assert=1 c_gen1_assert=1
c_s_axi_data_width=32 c_s_axi_addr_width=5
axi_timer/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_timer x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_count_width=32 c_one_timer_only=0
c_trig0_assert=1 c_trig1_assert=1 c_gen0_assert=1 c_gen1_assert=1
c_s_axi_data_width=32 c_s_axi_addr_width=5
axi_uartlite/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_uartlite x_ipversion=2.0 x_ipcorerevision=8 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_aclk_freq_hz=83250000 c_s_axi_addr_width=4
c_s_axi_data_width=32 c_baudrate=115200 c_data_bits=8 c_use_parity=0
c_odd_parity=0
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=5 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=design_1_lmb_bram_0.mem c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=16384 c_read_depth_a=16384 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=16384 c_read_depth_b=16384
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=16 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 19.3686 mW
clk_wiz_v5_1/1
iptotal=1 component_name=design_1_clk_wiz_0_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=3
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
lmb_bram_if_cntlr/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0000FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0xc0000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_bram_if_cntlr/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0000FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0x80000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_v10/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
lmb_v10/2
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
mig_7series_v2_3/1
iptotal=1 language=Verilog synthesis_tool=Vivado level=CONTROLLER
axi_enable=1 no_of_controllers=1 interface_type=DDR3 axi_enable=1
clk_period=3000 phy_ratio=4 clkin_period=6000 vccaux_io=1.8V
memory_type=COMP memory_part=mt41k128m16xx-15e dq_width=16 ecc=OFF
data_mask=1 ordering=NORM burst_mode=8 burst_type=SEQ
ca_mirror=OFF output_drv=LOW use_cs_port=1 use_odt_port=1
rtt_nom=40 memory_address_map=BANK_ROW_COLUMN refclk_freq=200 debug_port=OFF
internal_vref=1 sysclk_type=NO_BUFFER refclk_type=NO_BUFFER
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=7 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED c_family=artix7 c_ext_rst_width=4 c_aux_rst_width=4
c_ext_reset_high=1 c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1
c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
xlconcat/1
iptotal=1 x_ipproduct=Vivado 2015.1 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VERILOG
x_ipsimlanguage=MIXED in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in20_width=1 in21_width=1 in22_width=1
in23_width=1 in24_width=1 in25_width=1 in26_width=1
in27_width=1 in28_width=1 in29_width=1 in30_width=1
in31_width=1 dout_width=4 num_ports=4

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a35ticsg324-1L package=csg324 speedgrade=-1L version=2015.1
platform=nt64 temp_grade=industrial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=11.000000 pct_inputs_defined=7 user_junc_temp=27.7 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.8 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=6.8 (C/W)
user_board_temp=25.0 (C) junction_temp=27.7 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 toggle_rate=False signal_rate=False
static_prob=False read_saif=False on-chip_power=0.572476 dynamic=0.507899
effective_thetaja=4.8 thetasa=4.6 (C/W) thetajb=6.8 (C/W) off-chip_power=0.505912
clocks=0.951429 logic=0.022804 signals=0.032000 bram=0.038802
mmcm=0.000000 pll=0.000000 dsp=0.002551 i/o=0.258150
phaser=0.111052 xadc=0.003782 devstatic=0.064577 vccint_voltage=0.950000
vccint_total_current=0.169816 vccint_dynamic_current=0.162965 vccint_static_current=0.006851 vccaux_voltage=1.800000
vccaux_total_current=0.113585 vccaux_dynamic_current=0.102170 vccaux_static_current=0.011414 vcco33_voltage=3.300000
vcco33_total_current=0.002290 vcco33_dynamic_current=0.001290 vcco33_static_current=0.001000 vcco25_voltage=2.500000
vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco18_voltage=1.800000
vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco15_voltage=1.500000
vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco135_voltage=1.350000
vcco135_total_current=0.493701 vcco135_dynamic_current=0.492701 vcco135_static_current=0.001000 vcco12_voltage=1.200000
vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vccaux_io_voltage=1.800000
vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccbram_voltage=0.950000
vccbram_total_current=0.003453 vccbram_dynamic_current=0.002955 vccbram_static_current=0.000498 mgtavcc_voltage=1.000000
mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000
mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 vccadc_voltage=1.800000
vccadc_total_current=0.019600 vccadc_dynamic_current=0.001600 vccadc_static_current=0.018000 confidence_level_design_state=High
confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium confidence_level_device_models=Medium
confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=12232 slice_luts_fixed=0 slice_luts_available=20800 slice_luts_util_percentage=58.81
lut_as_logic_used=11143 lut_as_logic_fixed=0 lut_as_logic_available=20800 lut_as_logic_util_percentage=53.57
lut_as_memory_used=1089 lut_as_memory_fixed=0 lut_as_memory_available=9600 lut_as_memory_util_percentage=11.34
lut_as_distributed_ram_used=672 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=417 lut_as_shift_register_fixed=0
slice_registers_used=10756 slice_registers_fixed=0 slice_registers_available=41600 slice_registers_util_percentage=25.86
register_as_flip_flop_used=10754 register_as_flip_flop_fixed=0 register_as_flip_flop_available=41600 register_as_flip_flop_util_percentage=25.85
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=41600 register_as_latch_util_percentage=0.00
register_as_and_or_used=2 register_as_and_or_fixed=0 register_as_and_or_available=41600 register_as_and_or_util_percentage=<0.01
f7_muxes_used=196 f7_muxes_fixed=0 f7_muxes_available=16300 f7_muxes_util_percentage=1.20
f8_muxes_used=2 f8_muxes_fixed=0 f8_muxes_available=8150 f8_muxes_util_percentage=0.02
slice_used=3967 slice_fixed=0 slice_available=8150 slice_util_percentage=48.67
slicel_used=2709 slicel_fixed=0 slicem_used=1258 slicem_fixed=0
lut_as_logic_used=11143 lut_as_logic_fixed=0 lut_as_logic_available=20800 lut_as_logic_util_percentage=53.57
using_o5_output_only_used=4 using_o5_output_only_fixed= using_o6_output_only_used=8607 using_o6_output_only_fixed=
using_o5_and_o6_used=2532 using_o5_and_o6_fixed= lut_as_memory_used=1089 lut_as_memory_fixed=0
lut_as_memory_available=9600 lut_as_memory_util_percentage=11.34 lut_as_distributed_ram_used=672 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=4 using_o6_output_only_fixed=
using_o5_and_o6_used=668 using_o5_and_o6_fixed= lut_as_shift_register_used=417 lut_as_shift_register_fixed=0
using_o5_output_only_used=21 using_o5_output_only_fixed= using_o6_output_only_used=312 using_o6_output_only_fixed=
using_o5_and_o6_used=84 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=13792 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_util_percentage=66.31 fully_used_lut_ff_pairs_used=6925 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=1585 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=5282 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=510 minimum_number_of_registers_lost_to_control_set_restriction_used=1462(Lost)
memory
block_ram_tile_used=31 block_ram_tile_fixed=0 block_ram_tile_available=50 block_ram_tile_util_percentage=62.00
ramb36_fifo_used=31 ramb36_fifo_fixed=0 ramb36_fifo_available=50 ramb36_fifo_util_percentage=62.00
ramb36e1_only_used=31 ramb18_used=0 ramb18_fixed=0 ramb18_available=100
ramb18_util_percentage=0.00
dsp
dsps_used=6 dsps_fixed=0 dsps_available=90 dsps_util_percentage=6.67
dsp48e1_only_used=6
clocking
bufgctrl_used=9 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=28.13
bufio_used=0 bufio_fixed=0 bufio_available=20 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_fixed=1 mmcme2_adv_available=5 mmcme2_adv_util_percentage=40.00
plle2_adv_used=1 plle2_adv_fixed=1 plle2_adv_available=5 plle2_adv_util_percentage=20.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=10 bufmrce_util_percentage=0.00
bufhce_used=1 bufhce_fixed=0 bufhce_available=72 bufhce_util_percentage=1.39
bufr_used=0 bufr_fixed=0 bufr_available=20 bufr_util_percentage=0.00
specific_feature
bscane2_used=1 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=25.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=1 xadc_fixed=0 xadc_available=1 xadc_util_percentage=100.00
primitives
fdre_used=9943 fdre_functional_category=Flop & Latch lut6_used=3996 lut6_functional_category=LUT
lut3_used=2819 lut3_functional_category=LUT lut5_used=2475 lut5_functional_category=LUT
lut4_used=2212 lut4_functional_category=LUT lut2_used=1743 lut2_functional_category=LUT
ramd32_used=1018 ramd32_functional_category=Distributed Memory carry4_used=446 carry4_functional_category=CarryLogic
lut1_used=430 lut1_functional_category=LUT fdce_used=382 fdce_functional_category=Flop & Latch
fdse_used=350 fdse_functional_category=Flop & Latch rams32_used=322 rams32_functional_category=Distributed Memory
srlc32e_used=264 srlc32e_functional_category=Distributed Memory srl16e_used=230 srl16e_functional_category=Distributed Memory
muxf7_used=196 muxf7_functional_category=MuxFx fdpe_used=90 fdpe_functional_category=Flop & Latch
obuf_used=45 obuf_functional_category=IO oserdese2_used=43 oserdese2_functional_category=IO
ramb36e1_used=31 ramb36e1_functional_category=Block Memory obuft_used=19 obuft_functional_category=IO
ibuf_used=18 ibuf_functional_category=IO iserdese2_used=16 iserdese2_functional_category=IO
idelaye2_used=16 idelaye2_functional_category=IO ibuf_intermdisable_used=16 ibuf_intermdisable_functional_category=IO
bufg_used=9 bufg_functional_category=Clock srlc16e_used=7 srlc16e_functional_category=Distributed Memory
zhold_delay_used=6 zhold_delay_functional_category=Others dsp48e1_used=6 dsp48e1_functional_category=Block Arithmetic
oddr_used=5 oddr_functional_category=IO phaser_out_phy_used=4 phaser_out_phy_functional_category=IO
out_fifo_used=4 out_fifo_functional_category=IO obuftds_used=4 obuftds_functional_category=IO
ibufds_intermdisable_int_used=4 ibufds_intermdisable_int_functional_category=IO inv_used=3 inv_functional_category=LUT
phaser_in_phy_used=2 phaser_in_phy_functional_category=IO obufds_used=2 obufds_functional_category=IO
muxf8_used=2 muxf8_functional_category=MuxFx mmcme2_adv_used=2 mmcme2_adv_functional_category=Clock
in_fifo_used=2 in_fifo_functional_category=IO and2b1l_used=2 and2b1l_functional_category=Others
xadc_used=1 xadc_functional_category=Others plle2_adv_used=1 plle2_adv_functional_category=Clock
phy_control_used=1 phy_control_functional_category=IO phaser_ref_used=1 phaser_ref_functional_category=IO
idelayctrl_used=1 idelayctrl_functional_category=IO bufh_used=1 bufh_functional_category=Clock
bscane2_used=1 bscane2_functional_category=Others
io_standard
diff_sstl15_r=0 hstl_ii=0 lvcmos15=0 blvds_25=0
lvttl=0 diff_sstl15=0 hstl_i=0 diff_mobile_ddr=0
lvcmos33=1 mobile_ddr=0 lvcmos12=0 lvcmos25=0
pci33_3=0 hsul_12=0 lvcmos18=0 hstl_i_18=0
diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0 sstl18_ii=0
sstl15=0 sstl15_r=0 sstl135=1 sstl135_r=0
lvds_25=0 diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0
tmds_33=0 diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0
ppds_25=0 diff_sstl18_i=0 diff_sstl18_ii=0 diff_sstl135=1
diff_sstl135_r=0

router
usage
lut=13641 ff=10767 bram36=31 bram18=0
ctrls=510 dsp=6 iob=87 bufg=0
global_clocks=9 pll=1 bufr=0 nets=34130
movable_instances=28491 pins=170073 bogomips=0 high_fanout_nets=5
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=20078496 actual_expansions=15996222 router_runtime=89.370000

synthesis
command_line_options
-part=xc7a35ticsg324-1L -name=default::[not_specified] -top=design_1_wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=default::10000
-shreg_min_size=default::3 -mode=default::default -fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified]
-resource_sharing=default::auto -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:13:14s memory_peak=1463.918MB memory_gain=1126.945MB hls_ip=0