################################################################ # This is a generated script based on design: isolation_config # # Though there are limitations about the generated script, # the main purpose of this utility is to make learning # IP Integrator Tcl commands easier. ################################################################ namespace eval _tcl { proc get_script_folder {} { set script_path [file normalize [info script]] set script_folder [file dirname $script_path] return $script_folder } } variable script_folder set script_folder [_tcl::get_script_folder] ################################################################ # Check if script is running in correct Vivado version. ################################################################ set scripts_vivado_version 2017.1 set current_vivado_version [version -short] if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { puts "" catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} return 1 } ################################################################ # START ################################################################ # To test this script, run the following commands from Vivado Tcl console: # source isolation_config_script.tcl # If there is no project opened, this script will create a # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. set list_projs [get_projects -quiet] if { $list_projs eq "" } { create_project project_1 myproj -part xczu9eg-ffvb1156-2-i set_property BOARD_PART xilinx.com:zcu102:part0:3.0 [current_project] } # CHANGE DESIGN NAME HERE set design_name isolation_config # If you do not already have an existing IP Integrator design open, # you can create a design using the following command: # create_bd_design $design_name # Creating design if needed set errMsg "" set nRet 0 set cur_design [current_bd_design -quiet] set list_cells [get_bd_cells -quiet] if { ${design_name} eq "" } { # USE CASES: # 1) Design_name not set set errMsg "Please set the variable to a non-empty value." set nRet 1 } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { # USE CASES: # 2): Current design opened AND is empty AND names same. # 3): Current design opened AND is empty AND names diff; design_name NOT in project. # 4): Current design opened AND is empty AND names diff; design_name exists in project. if { $cur_design ne $design_name } { common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." set design_name [get_property NAME $cur_design] } common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { # USE CASES: # 5) Current design opened AND has components AND same names. set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 1 } elseif { [get_files -quiet ${design_name}.bd] ne "" } { # USE CASES: # 6) Current opened design, has components, but diff names, design_name exists in project. # 7) No opened design, design_name exists in project. set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." set nRet 2 } else { # USE CASES: # 8) No opened design, design_name not in project. # 9) Current opened design, has components, but diff names, design_name not in project. common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." create_bd_design $design_name common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." current_bd_design $design_name } common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." if { $nRet != 0 } { catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} return $nRet } ################################################################## # DESIGN PROCs ################################################################## # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. proc create_root_design { parentCell } { variable script_folder if { $parentCell eq "" } { set parentCell [get_bd_cells /] } # Get object for parentCell set parentObj [get_bd_cells $parentCell] if { $parentObj == "" } { catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} return } # Make sure parentObj is hier blk set parentType [get_property TYPE $parentObj] if { $parentType ne "hier" } { catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} return } # Save current instance; Restore later set oldCurInst [current_bd_instance .] # Set parent object as current current_bd_instance $parentObj # Create interface ports set dip_switches_8bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 dip_switches_8bits ] # Create ports # Create instance: axi_gpio_0, and set properties set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] set_property -dict [ list \ CONFIG.GPIO_BOARD_INTERFACE {dip_switches_8bits} \ CONFIG.USE_BOARD_FLOW {true} \ ] $axi_gpio_0 # Create instance: ps8_0_axi_periph, and set properties set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ] set_property -dict [ list \ CONFIG.NUM_MI {1} \ ] $ps8_0_axi_periph # Create instance: rst_ps8_0_99M, and set properties set rst_ps8_0_99M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_99M ] # Create instance: zynq_ultra_ps_e_0, and set properties set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.0 zynq_ultra_ps_e_0 ] set_property -dict [ list \ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15} \ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \ CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \ CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_IO {