/*
 * Clock specification for Xilinx ZynqMP
 *
 * (C) Copyright 2015, Xilinx, Inc.
 *
 * Michal Simek <michal.simek@xilinx.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */


&amba {
	clk100: clk100 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	clk125: clk125 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
	};

	clk200: clk200 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <200000000>;
	};

	clk250: clk250 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <250000000>;
	};

	clk300: clk300 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <300000000>;
	};

	clk600: clk600 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <600000000>;
	};

	pss_ref_clk: pss_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <33333333>;
	};

	video_clk: video_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	pss_alt_ref_clk: pss_alt_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	gt_crx_ref_clk: gt_crx_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <108000000>;
	};

	aux_ref_clk: aux_ref_clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <27000000>;
	};

	dp_aclk: clock0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-accuracy = <100>;
	};

	dp_aud_clk: clock1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <24576000>;
		clock-accuracy = <100>;
	};

	dpdma_clk: dpdma_clk {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <533000000>;
	};

	drm_clock: drm_clock {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <262750000>;
		clock-accuracy = <0x64>;
	};

	clkc: clkc@ff5e0020 {
		#clock-cells = <1>;
		compatible = "xlnx,zynqmp-clkc";
		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
		clock-output-names = "iopll", "rpll", "apll", "dpll",
				"vpll", "iopll_to_fpd", "rpll_to_fpd", "apll_to_lpd", "dpll_to_lpd",
				"vpll_to_lpd", "acpu", "acpu_half", "dbf_fpd", "dbf_lpd", "dbg_trace",
				"dbg_tstmp", "dp_video_ref", "dp_audio_ref", "dp_stc_ref", "gdma_ref",
				"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref", "gpu_ref",
				"gpu_pp0_ref", "gpu_pp1_ref", "topsw_main", "topsw_lsbus",
				"gtgref0_ref", "lpd_switch", "lpd_lsbus", "usb0_bus_ref",
				"usb1_bus_ref", "usb3_dual_ref", "usb0", "usb1", "cpu_r5",
				"cpu_r5_core", "csu_spb", "csu_pll", "pcap", "iou_switch",
				"gem_tsu_ref", "gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref", "gem3_ref",
				"gem0_tx", "gem1_tx", "gem2_tx", "gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
				"uart0_ref", "uart1_ref", "spi0_ref", "spi1_ref",
				"nand_ref", "i2c0_ref", "i2c1_ref", "can0_ref", "can1_ref", "can0", "can1", "dll_ref",
				"adma_ref", "timestamp_ref", "ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
	};

};
&can0 {
	clock-names = "can_clk", "pclk", "pll";
	clocks = <&clkc 16>, <&clkc 31>, <&clkc 4>;
};

&can1 {
	clock-names = "can_clk", "pclk", "pll";
	clocks = <&clkc 16>, <&clkc 31>, <&clkc 4>;
};

&fpd_dma_chan1 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan2 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan3 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan4 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan5 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan6 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan7 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&fpd_dma_chan8 {
	clocks = <&clkc 19>, <&clkc 31>;
};

&nand0 {
	clocks = <&clkc 60>, <&clkc 31>;
};

&gem0 {
	clocks = <&clkc 45>, <&clkc 45>, <&clkc 49>;
	clock-names = "pclk", "tx_clk", "hclk";
};

&gem1 {
	clocks = <&clkc 46>, <&clkc 46>, <&clkc 50>;
	clock-names = "pclk", "tx_clk", "hclk";
};

&gem2 {
	clocks = <&clkc 47>, <&clkc 47>, <&clkc 51>;
	clock-names = "pclk", "tx_clk", "hclk";
};

&gem3 {
	clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>;
	clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
};

&gpio {
	clocks = <&clkc 31>;
};

&i2c0 {
	clocks = <&clkc 61>;
};

&i2c1 {
	clocks = <&clkc 62>;
};

&qspi {
	clocks = <&clkc 53>, <&clkc 31>;
	/* Don't know the per/interface clock hacking to give main clock */
};

&sata {
	clocks = <&clkc 22>;
};

&sdhci0 {
	clocks = <&clkc 54>, <&clkc 31>;
};

&sdhci1 {
	clocks = <&clkc 55>, <&clkc 31>;
};

&spi0 {
	clocks = <&clkc 58>, <&clkc 31>;
};

&spi1 {
	clocks = <&clkc 59>, <&clkc 31>;
};

&uart0 {
	clocks = <&clkc 56>,  <&clkc 31>;
};

&uart1 {
	clocks = <&clkc 57>,  <&clkc 31>;
};

&usb0 {
	clocks = <&clkc 32>,  <&clkc 31>;
};

&usb1 {
	clocks = <&clkc 33>,  <&clkc 36>;
};

&xilinx_drm {
	clock-names = "pclk", "pll";
	clocks = <&clkc 16>, <&clkc 4>;
};

&xlnx_dp {
	clocks = <&dp_aclk>, <&dp_aud_clk>;
};

&xlnx_dpdma {
	clocks = <&dpdma_clk>;
};

&watchdog0 {
	clocks = <&clk125>;
};

&xlnx_dp_snd_codec0 {
	clocks = <&dp_aud_clk>;
};