/dts-v1/; / { #address-cells = <0x02>; #size-cells = <0x02>; passthrough { compatible = "simple-bus"; ranges; #address-cells = <0x02>; #size-cells = <0x02>; clk: clk { #clock-cells = <0x0>; clock-frequency = <0x1fc9350>; compatible = "fixed-clock"; }; clock-controller { #clock-cells = <0x1>; compatible = "fixed-clock"; clocks = <0xb 0xc 0xd 0xe 0xf>; clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk"; phandle = <0x4>; }; pcie@fd0e0000 { compatible = "xlnx,nwl-pcie-2.11"; status = "okay"; #address-cells = <0x3>; #size-cells = <0x2>; #interrupt-cells = <0x1>; msi-controller; device_type = "pci"; interrupt-parent = <0xfde8>; interrupts = <0x0 0x76 0x4 0x0 0x75 0x4 0x0 0x74 0x4 0x0 0x73 0x4 0x0 0x72 0x4>; interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <0x20>; reg = <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd480000 0x0 0x1000 0x80 0x0 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x2000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000 0x43000000 0x6 0x0 0x6 0x0 0x2 0x0>; interrupt-map-mask = <0x0 0x0 0x0 0x7>; bus-range = <0x0 0xff>; interrupt-map = <0x0 0x0 0x0 0x1 0x21 0x1 0x0 0x0 0x0 0x2 0x21 0x2 0x0 0x0 0x0 0x3 0x21 0x3 0x0 0x0 0x0 0x4 0x21 0x4>; assigned-clocks = <&clk>; clocks = <&clk &clk &clk &clk &clk>; xlnx,bar0-enable = <0x0>; xlnx,bar1-enable = <0x0>; xlnx,bar2-enable = <0x0>; xlnx,bar3-enable = <0x0>; xlnx,bar4-enable = <0x0>; xlnx,bar5-enable = <0x0>; xlnx,pcie-mode = "Root Port"; xlnx,tz-nonsecure = <0x0>; phandle = <0x20>; xen,path = "/axi/pcie@fd0e0000"; xen,reg = <0x80 0x00000000 0x0 0x10000000 0x80 0x00000000>, <0x0 0xfd0e0000 0x0 0x1000 0x0 0xfd0e0000>, <0x0 0xfd480000 0x0 0x1000 0x0 0xfd480000>; legacy-interrupt-controller { interrupt-controller; #address-cells = <0x0>; #interrupt-cells = <0x1>; phandle = <0x21>; }; }; }; };