Zynq UltraScale MPSoC Base TRD 2018.1 - Design Module 8

Zynq UltraScale MPSoC Base TRD 2018.1 - Design Module 8

Design Overview


This module shows how to move the 2D convolution filter from software to hardware using the PL optimized xfopencv library that provides an OpenCV equivalent function.





Design Components


This module requires the following components:
  • zcu102_base_trd (SDSoC)
  • filter2d (accelerator)
  • sdxfilter2d (gstreamer plugin)
  • video_qt2
    • video_lib
    • gst_lib



Build Flow Tutorials


2D Filter Sample and GStreamer Plugin


This tutorial shows how to build the 2D filter sample with HW acceleration based on the Base TRD SDSoC platform.

  • Set the build environment variables. This requires that you have previously completed the PetaLinux SDK installation step from DM5.
    Note 1: Make sure you set the env variables in the same shell that is used to launch SDx. Also make sure the env variables are set before starting SDx, otherwise close and re-start SDx.
    Note 2: The below command might ask you execute unset LD_LIBRARY_PATH and then re-execute the command. Go ahead and follow those steps.
    % source $TRD_HOME/petalinux/sdk/environment-setup-aarch64-xilinx-linux
  • Open the existing SDx workspace from design module 7 using the SDx tool.
    % cd $TRD_HOME/workspaces/ws_f2d
    % sdx -workspace . &&
  • In the "Application Project Settings" panel, set the active build configuration to "Debug" which will bring back the pre-selected Hardware Functions marked for acceleration. Make sure the functions are listed as shown in the figure and the 'Generate bitstream' and 'Generate SD card image' boxes are checked.
  • Right-click the filter2d project in the explorer pane and select 'Build Project'. This can take several hours. Copy the generated SD card image once the build is finished.
    % cp -rf filter2d/Debug/sd_card $TRD_HOME/sd_card/dm8
  • Copy the generated libraries and the plugin assuming the project was previously built in DM7.
    % mkdir -p $TRD_HOME/sd_card/dm8/lib $TRD_HOME/sd_card/dm8/gstreamer-1.0
    % cp gst/allocators/Debug/libgstsdxallocator.so gst/base/Debug/libgstsdxbase.so $TRD_HOME/sd_card/dm8/lib
    % cp gst/plugins/filter2d/Debug/libgstsdxfilter2d.so $TRD_HOME/sd_card/dm8/gstreamer-1.0

Video Qt Application


There is no need to rebuild the video_qt2 application if you have already built it in module 7, otherwise follow the instructions from module 7.

  • Copy the generated video_qt2 executable to the dm8 SD card directory.
    % cp $TRD_HOME/workspaces/ws_video/video_qt2/video_qt2 $TRD_HOME/sd_card/dm8



Run Flow Tutorial


  • See here for board setup instructions.
  • Copy all the files from the $TRD_HOME/sd_card/dm8 SD card directory to a FAT formatted SD card.
  • Power on the board to boot the images; make sure INIT_B, done and all power rail LEDs are lit green.
  • After ~30 seconds, the display will turn on and the application will start automatically, targeting the max supported resolution of the monitor (one of 3840x2160 or 1920x1080 or 1280x720). The application will detect whether DP Tx or HDMI Tx is connected and output on the corresponding display device.
  • To re-start the TRD application with the max supported resolution, run
    % run_video.sh
  • To re-start the TRD application with a specific supported resolution use the -r switch e.g. for 1920x1080, run
    % run_video.sh -r 1920x1080
  • The user can now control the application from the GUI's control bar (bottom) displayed on the monitor.
  • The user can select from the following video source options:
    • TPG (SW): virtual video device that emulates a USB webcam purely in software
    • USB: USB Webcam using the universal video class (UVC) driver
    • TPG (PL): Test Pattern Generator implemented in the PL
    • HDMI: HDMI input implemented in the PL
    • CSI: MIPI CSI image sensor input implemented in the PL
    • File: Raw video file source
  • The user can select from the following accelerator options:
    • Passthrough (no accelerator)
    • 2D convolution filter with configurable coefficients
  • The supported accelerator modes depend on the selected filter:
    • SW - accelerator is run on A53
    • HW - accelerator is run on PL
  • The video info panel (top left) shows essential settings/statistics.
  • The CPU utilization graph (top right) shows CPU load for each of the four A53 cores.



Continue with Design Module 9.
Return to the Design Tutorials Overview.

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy