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Protocol “AXI4-Lite”, mode “system init”: these two settings allow to write a few registers when de-asserting the reset. The core is very light weight in this configuration.
Ch-1 Base Address and High Address: These two addresses must correspond to the RFDC IP addresses. In this case, 0x44b00000 and 0x44b3ffff.
Address and Data COE files: The two files initialize the small memory in the AXI traffic generator with the address and data to write. To shutdown one DAC tile, 0x3 must be written into the restart state register (offset 0x8) followed by 0x1 into the Restart Power-On State Machine Register (offset 0x4). Each tile address is offset at Tile_Id*0x4000.
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AXI interconnect settings
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